Hi, I'm trying to reimplement the design at in Verilog, targetting a Xilinx CPLD. Problem is, I've got all the GAL equations translated, but I can't work out how to handle the latches and buffers. Why am I doing this? Because I'm out of 74LS chips and all my suppliers are closed until Monday...
Basically, when /LDW goes active, the top-right '574 latches in the data on D[0..7]. When /UDW goes active, the bottom-right '244 passes the data on D[0..7] straight onto ID[8..15] and the top-right '574's output is enabled. Reading is fairly simple too - /LDR goes active, the bottom-left '574 latches ID[8..15] and the top-left '245 passes the data on ID[0..7] onto D[0..7]. When /UDR goes active, the '244 is inactive and the '574's output gets enabled (ID[8..15] data gets popped onto the D[0..7] bus). Pretty simple on paper.
How would you go about modelling this circuit in Verilog? Can anyone offer me some hints or suggestions?
Thanks,