SI considerations for single chip memory configurations

Sep 02, 2005 1 Replies
M

Hello,



I'm designing a board with DDR and QDR II memories. When I look at the memory design reference of the FPGA manufacturers, all the signals are terminated by resistors. But when I look at the memory manufacturers app notes they say that in the case of single memory chip (point to point) configuration only a source resistor is needed. As modern FPGAs have builtin controlled source impedance there should be not resistor at all. (QDRII memories have controlled drivers too)



So who is right here? (And yes, I will have the design simulated before producing the boards anyway ;-)



Marc


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J

Dealers' choice. (designers' choice, actually) Your simulations will show you what looks "good" but if QDR II has the same on-die terminations for SSTL style signals like DDR II does, the point-to-point can be happy with one end terminated as long as the traces are short.

Some FPGAs don't have convenient source resistors available, either as series resistors or as source-parallel terminations to Vcco/2.

You just need valid logic levels (sometimes requiring a load) and rise times that are several times the round trip delay of your circuit path. If you have those, terminations aren't needed for SI reasons as your SI tools will show.

builtin

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