Hello,
I'm designing a board with DDR and QDR II memories. When I look at the memory design reference of the FPGA manufacturers, all the signals are terminated by resistors. But when I look at the memory manufacturers app notes they say that in the case of single memory chip (point to point) configuration only a source resistor is needed. As modern FPGAs have builtin controlled source impedance there should be not resistor at all. (QDRII memories have controlled drivers too)
So who is right here? (And yes, I will have the design simulated before producing the boards anyway ;-)
Marc