Latest threads in Field-Programmable Gate Arrays

Modelsim XE and multi-file Verilog projects

Hi, I'm currently designing a disc drive controller to interface with a 6502-based system. To ease the design a little,...

4 21yrs

philpem

4 21yrs philpem

FIFO PhysDesignRules:993

Just curious if anyone else has come across this: I have a design using an asynchronous fifo. It builds without any pro...

0 21yrs

maplante

0 21yrs maplante

Xilinx Virtex II fpga - providing single ended signal to lvds defined pin

Hello, I am having ADI board containing xilinx virtex II chip. There are two pins defined as LVDS_33 I/O but I wanted t...

0 21yrs

tucsondude

0 21yrs tucsondude

current!

We have a 3.3 volt uP that's programming two Spartan 3 FPGAs in slave serial mode. A CPU port pin drives a 180 ohm seri...

3 21yrs

jjlarkin

3 21yrs jjlarkin

MicroBlaze: PLX PCI 9056 IP

Has anyone seen or developed an IP to interface the Microblaze to the PLX PCI 9056 in mode C? Thanks, JTW

0 21yrs

Spartan3 PCI SSO(Simultaneously Switching Output) problem

Hi All! I have a project which will use spartan3 xc3s200-pq208 as an pci bridge chip. And there's the problem: In spart...

11 21yrs

huangjielg

11 21yrs huangjielg

Strange behaviour while trying to program MAX II CPLD's

Hi group, My design contains 1 MAXII EPM1270, 1 LXT971, 1 LXT971, 1 MAXII EPM1270 in series in a JTAG chain. Of course,...

1 21yrs

abeaujean

1 21yrs abeaujean

Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform level signal connect.

I've just started to use the XUP Virtex-II Pro, but I hit a problem I can't seem to solve or circumvent: I'm using EDK...

2 21yrs

zoinks

2 21yrs zoinks

"Perform Timing-Driven Packing and Placement" error?

Hello, I am using the Xilinx ISE 7.1 with ModelSim 6.0a and I have a problem when I use the "Perform Timing-Driven Pack...

4 21yrs

M.G.v.d.Horst

4 21yrs M.G.v.d.Horst

New FPGA development board.

Working for a manufacturing company that specialises in FPGA designs and development boards, I can now tell you that ou...

0 21yrs

ian

0 21yrs ian

A strange behavior

Hallo, I have made a small microcontroller based on microblaze. I have connected a differential 16 bit adc to my system...

2 21yrs

marcotoschi

2 21yrs marcotoschi

bare die (non packaged) FPGA, CPLD, controllers ?

Who sells bare die (non packaged) FPGA, CPLD, controllers ? Thanks. Dix www.testhaus.com

4 21yrs

dieter.tank

4 21yrs dieter.tank

CPLD CoolRunner-II - IO current limited to 8mA?

Hello, I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512). But from the datasheet I get that the curr...

4 21yrs

denizdikmen

4 21yrs denizdikmen

Discrepancies in area estimation (Precision RTL vs Xilinx ISE Map)

Dear all, I'd like to understand why my design, which occupies 2500 Slice according to Precision RTL, increases to 3900...

1 21yrs

giachella.g

1 21yrs giachella.g

Mentor FPGA Advantage, a simple question

I'm using Mentor Fpga Advantage 7.0 and really, I read the docs but I can't figure the difference between "through bloc...

2 21yrs

fake

2 21yrs fake

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