Hey Folks, i have a question about the RAM instantiations for the Spartan 3(XC3S200) in the Xilinx verilog templates. You can instantiate different types of SRAM sizes and bit widths, like 16K x 1, 2K x 8,
512K x 32, but what if a user wants use the SRAM in a 256K x 16 format, or something else not displayed in the templates?. Can this be done ??
Also, the clock parameter (clk) in the instantiations, does this neeed to be 100 Mhz, same as the SRAM clock frequency?. Do i need to use the DCM to double the FPGA clock frequency?.
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The templates are just the basic primitives that represent 1 BRAM in different configurations. If you need larger RAM arrays, you have to combine multiple BRAMs by hand. Or use Core generator.
?? Dunno about this. I guess it's just for simulation.
The individual BlockRAMs can go to 512x32, not 512kx32 (512x36, actually, thanks to the available undedicated parity bits). To get 256k x 32, you'd need about 256 BlockRAMs which wouln''t come close to fitting in an XC3S200. If you mean 256x32, you just need to instantiate one 512x36 and tie the MSbit of the address to 0.
Both ports are read and/or write. Each port requires a clock for the operation to occur. There is no "SRAM clock frequency" but a frequency for the access at each port. This can be 100 MHz, 200 MHz, 50 MHz.... what are your needs? This determines which clocks you feed to the BlockRAMs.
If you need 512kBytes, you need an external memory, no ways around it.
Hi John, basically, every 1ms (very slow) a 16 bit value is coming in from an ADC. I need to take this value and put it in memory. The Spartan 3 has 262,144(18 bit) 16 bit wide memory slots (two of). I just want to insert the ADC data in memory location one, increment the address, wait for the next ADC value and put it in memory address two...so on. I have written code for this in verilog but i was looking at maybe instantiating it using one of the xilinx templates, because my code is messy. Is there any better strategy for what i am doing?. ....Thanks !!!!!!!!!
The Xilinx XC3S200 FPGAs do not have that much memory on chip. The memory is in blocks of 16K (or 18K with parity) bits. You can select different configurations for each block, but the total size of each block is fixed at 16K/18K bits. This is 2K bytes.
The XC3S200 has 12 blocks, for a total of 24K bytes. If you have data that is 16 bit, then at most, you can store 12K values.
There is detailed comparison information on all Xilinx FPGAs at this URL:
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No it doesn't. It has a total of 221184 bits.
If you really need 256K x 16 storage, it will need more memory, off chip. How this is implemented is up to you. The Xilinx templates only cover what fits on chip.
=================== Philip Freidin snipped-for-privacy@fpga-faq.org Host for
You should be able to store up to 12k samples in the XC3S200 as Philip Freidin pointed out.
As for the clock, the clock you use to manipulate the ADC information should be sufficient. If you're using a 100 MHz system clock to control the interface to the ADC, use that for the RAM, too. Simply provide the EN (for read or rd/wr) and WE (combined with EN for write) to strobe the data in.
You can use dual-port memories to access the ADC data separate from the writing of that data so the addressing doesn't ahve to be muxed between the sequential write and a random read.
Note that many synthesizers will do a fine job of inferring a 2kx16 memory with separate read and write addresses though some synthesizers want to see only one clock even though the dual-port BlockRAMs can have independent read and write clocks.
Your code should end up looking messier with instantiations but you would have significantly better control if you want to do anything slightly unusual.
Hey John, thanks for all the information and i will try that piece of code you have given me, but how do i assign the FPGA pins to reg [15:0] ADCvals [12287:0]; . Its basically - [data_in]ADCvals[inAddr]. DO i just have to assign the "inAddr" to the SRAM address pins and not worry about the data pins?. Also, can "inAddr" and "rdAddr" be incrementing numbers?. I want to start at memory address 0 and store the incoming data up to 12,000. Once completed, i want to start at 0 again and send out the data until i reach memory address 12,000. I was hoping to just have an number that increments, something like this,
The "[15:0] ADCvals[i]" isn't correct syntax. If ADCvals is defined as "reg [15:0] ADCvals [12287:0]" then the [15:0] is implied but can be made explicit with most Verilog2001-capable tools by "ADCvals[i][15:0]
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