Hi :
I am just completing a control system implemented on a Cyclone using Quartus, entirely in schematic with loads of Mega Functions.
The chip is getting full. When I look at a the resource usage, it is noticeable how much the many 12x12 signed multipliers are using. I played with the pipelining option in Mega Wizard, but after adding a pipe of 1, no further reduction in LE count is obtained by additional pipelining (I guess it's the same implementation with post latching).
So what I plan to do is implement a signed 12x12 long multiply (probably as an unsigned block with absoluting, saturating and re-signing functions around it)
I can picture the schematic for doing this in my mind (4x4 multiply(maybe as a LUT), 24 bit accumulator and a state-counter controlled muxing scheme to allocate "x16^n" shifting to the 9 multiplicands as they are accumulated)
Whilst I do enjoy re-inventing the wheel, it occurs to me that someone must have a VHDL implementation of this somewhere.
Can anybody point me at VHDL code for this ?
Thanks Gary