Field-Programmable Gate Arrays

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Block RAM problem (spartan 3)

Hey i have spartan 3 and i wanna know about Block RAM available with it.from xilinx website i came to know that i have...
0 comments posted 21yrs
posted by ni.neofpga
0 comments posted 21yrs posted by ni.neofpga

Which JTAG cable for Xilinx & Linux?

Hi, I have an old Xilinx XChecker Serial cable which has served me well. Apparently (not that I can tell) and unfortuna...
3 comments posted 21yrs
posted by r_fpga_dev
3 comments posted 21yrs posted by r_fpga_dev

future of antifuse fpgas?

Does anybody have a general feel for whether or not Actel (or any other vendor) is going to bring out a new generation...
8 comments posted 21yrs
posted by megacz
8 comments posted 21yrs posted by megacz

creating a custom opb bus master

Hello fpga-faq, I want to create a user module that will act as a master on an opb bus. I am using xilinx Platform Stud...
3 comments posted 21yrs
posted by arincm
3 comments posted 21yrs posted by arincm

compedklib error

I am trying to compile edk libraries( EDK 7.1 on Fedora Core 2) .I followed the "simulation in edk" instructions and us...
0 comments posted 21yrs
posted by nitesh.guinde
0 comments posted 21yrs posted by nitesh.guinde

implementing the tristate bus

Hello Guys, I am having an IP which has 2 interface master and slave interface but there single external bus. To adapt...
3 comments posted 21yrs
posted by stud_lang_jap
3 comments posted 21yrs posted by stud_lang_jap

Post synthesis simulation errors

Hi, I performed a post route simulation using FPGA Advantage tools and Modelsim 6.0c. The place and route process ended...
8 comments posted 21yrs
posted by giovanniparodi79
8 comments posted 21yrs posted by giovanniparodi79

Reading a PAL fusemap with a microscope

I sent a PAL to MEFAS to be decapped. They e-mailed me this picture of the die before they sent it back. I just receive...
16 comments posted 21yrs
posted by grant
16 comments posted 21yrs posted by grant

Timing Violation Quartus "__Z" issue

In Quartus for the timing report have you ever gotten a timing violation to/from a signal ending with __Z - defining a...
0 comments posted 21yrs
posted by archilleswaterland
0 comments posted 21yrs posted by archilleswaterland

EDK 7.1 simulation

I tried to comiple the xilinx and EDK librariess for the first time by using the simulation library compilation wizard....
0 comments posted 21yrs
posted by nitesh.guinde
0 comments posted 21yrs posted by nitesh.guinde

Microblaze and LMB

Hello all, I am designing a communications board based on a microblaze implementes on a spartan 3 400. I have 512kx32 e...
2 comments posted 21yrs
posted by yozara
2 comments posted 21yrs posted by yozara

digilent web site?

It has been down for two days now. Anyone know the story?
1 comments posted 21yrs
posted by pfraser
1 comments posted 21yrs posted by pfraser

Quartus II - Timing Analyzer

Hi, I am new to the Quartus II software and have trouble configuring the timing analyzer, would appreciate if anyone ca...
2 comments posted 21yrs
posted by sanjay.gajendra
2 comments posted 21yrs posted by sanjay.gajendra