Hello all,
I am designing a communications board based on a microblaze implementes on a spartan 3 400.
I have 512kx32 external synchronous RAM, and I am trying to connect it to the microblaze by the LMB, both to data and instruction sides, so I have to multiplex both buses, giving priority to instruction bus. All this is easy and I have done it. Well, it seemed easy.
When I test the external memorys, everything goes fine except when the interruption to MB activates one cycle before a memory read, so thtat INTERRUPT_TAKEN acknowledges the interrupt some 4-5 cycles after that (it is not a variable amount, it is fixed biut I have closed the chipscope window before writing this).
Now at last, the *problem* or, as the C++ experts say the Really Bad Thing TM. Whenever this interlave of interrupt and memory fetch happens, register R14 does not save PC, but gets the value 0x00000000, thus causing a reset after the interrupt attention routine.
By the way, all interrupt code and data lies within BRAM, and the external RAM cycle presents no anomalies, it end correctly.
Has anyone any information to guide me to solution, or will I be forced to connect a fast synchronous RAM to OPB, thus working at half speed?
Thanks to all
Juan A. Zaratiegui