Quartus II - Timing Analyzer


I am new to the Quartus II software and have trouble configuring the timing analyzer, would appreciate if anyone can help me out.. Below is what I need.

My design includes an incoming clock of 122Mhz (clk0) that is then divided into 61Mhz (clk1) and 30Mhz (clk2) using a built-in PLL. Depending on two input pins (S0, S1) one of the three clocks is used to drive the main logic i.e. the main logic is still a single clock design.

How do I tell the timing analyzer not to treat the main logic as a multiclock design, and prevent it from throwing tco and fmax violations? I get no errors if I removed the dynamic selection of clocks (between clk0, clk1 and clk2) and force the main logic to run at a given clock.



Reply to
Loading thread data ...

You need to use multi-cycle contraints!

Regards, Mark

Reply to
Mark McDougall

There are three options from easy to hard:

1.- It is very likely that all you need to do is CUT all multi-clock transfers. This is easily done by making a clock to clock CUT

set_instance_assignment -from clk1 -to clk2 -name CUT ON set_instance_assignment -from clk2 -to clk1 -name CUT ON and so on.

This will at least ensure Quartus Timing Analyzer (TAN) does not try to do a multi-clock analysis (e.g. use clk1 for the source register and clk2 to the destination register):

2.- If this is not enough, the second solution is to simply pick one clock (likely the fastest clock) as the clock use by TAN. To do this, just add a CUT to the other two clocks

set_instance_assignment -to clk1 -name CUT ON set_instance_assignment -to clk2 -name CUT ON

3.- The last possibility is to simply add a base clock on the output of the MUX which I assume is used to select the clocks. This is ok for FMax (i.e. internal reg to reg transfers), but will not work on Tco as Tco is defined as an clock pin to output pin path, and does not account for internal clocks. A workaround is to change the Tco to an OUTPUT_MAX_DELAY assignment which can be set from the internal clock. For information on OUTPUT_MAX_DELAY see

formatting link

Hope this helps, Subroto Datta Altera Corp.

Reply to
Subroto Datta

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.