I am new to the Quartus II software and have trouble configuring the timing analyzer, would appreciate if anyone can help me out.. Below is what I need.
My design includes an incoming clock of 122Mhz (clk0) that is then divided into 61Mhz (clk1) and 30Mhz (clk2) using a built-in PLL. Depending on two input pins (S0, S1) one of the three clocks is used to drive the main logic i.e. the main logic is still a single clock design.
How do I tell the timing analyzer not to treat the main logic as a multiclock design, and prevent it from throwing tco and fmax violations? I get no errors if I removed the dynamic selection of clocks (between clk0, clk1 and clk2) and force the main logic to run at a given clock.