I have converted an old Xilinx schematic design into VHDL. However, I'm
running into a problem with how to implement the GSR function properly.
I'm used to having an external reset line feed one of the pins, that could be specified to Leonardo 4.22 as the global_sr signal. This design, however, used an internally generated pulse from the configuration section to pulse the registers.
When I try to read in the design, I get told by Leonardo that the GSR net name that I'm using does not have a source --> looking at the schematic viewer, I find that all of the GSR nets get grounded.
Any thoughts on how I can resolve this issue are welcomed. I'm going to review the older Leonardo documentation, as well as look at the Xilinx docs regarding the STARTUP block. (One of the things, however, is that the Leonardo docs state NOT to instantiate the BSCAN or STARTUP block -- which I'm not sure about).
Regards, Bob