Post synthesis simulation errors

If your functional sim works as expected and your design is synchronous and you pass post-route static timing, no sdf sim of the routed netlist is really needed.

If you want to try one anyway, start with a simpler example.

-- Mike Treseler

MIke -

If you're trying to track down a synthesis bug, post synthesis simulation may be useful.

I've seen case in the past where XST produced inccorect logic. A slight change to the Verilog structure and the bug disappeared. In cases like that, gate level sims are useful.

In general, I don't do gate level sims, I pay attention to the the constraints and the static timing results.

John Providenza

Was the SDF file applied to the back annotated VHDL or verilog file, or the the source file? The SDF file has timing information for the back annotated file, not for the source file.

GTS is part of the startup logic, which isn't part of your source. While I can't be sure without looking at all of the files, I'd suspect that this is related to GTS_OR.

I'm going to

-- Caution: Contents may contain sarcasm. Phil Hays

The SDF is applied to the backannotated Verilog. Thanks for your indication about GTS, but it seems that your response has been stopped by something / someone, you are going to...? Thanks for any help Gio

The pre-route Verilog? Or the post-route Verilog?

I also had similar problem before. Problem was not the design itself, but the 'test bench'. Maybe your problem is somewhere in test bench, for example, name of component, how to instantiate it.

The post route verilog (it starts as follow the following)

// Xilinx Verilog netlist produced by netgen application (version G.30) // Command : -sim -ofmt verilog -sdf_anno true -w -s 8 FIOS_with_FSM_out // Input file : FIOS_with_FSM_out.ncd // Output file : FIOS_with_FSM_out.v // Design name : FIOS_with_FSM // # of Modules : 1 // Xilinx : /mentor/software/xilinx // Device : v300efg456-8 (PRODUCTION 1.69 2003-12-13)

// This verilog netlist is a simulation model and uses simulation // primitives which may not represent the true implementation of the // device, however the netlist is functionally correct and should not // be modified. This file cannot be synthesized and should only be used

// with supported simulation tools.

`timescale 1 ns/1 ps

module FIOS_with_FSM ( CLK, READY, RESET, S_parameter );

The post place and route module is:

module FIOS_with_FSM ( CLK, READY, RESET, S_parameter);

and the testbench is as follows:

`resetall `timescale 1ns/10ps

module test_FIOS_with_FSM ; // Inputs reg CLK; reg RESET; reg [7:0]S_parameter;

// Outputs wire READY;

// Instantiate the Unit Under Test (UUT) FIOS_with_FSM uut ( .CLK(CLK), .RESET(RESET), .READY(READY), .S_parameter(S_parameter) );

//////////////////////////////////////////////////////////////////////////////// initial CLK = 1'b0; //set clk to 0 always #25 CLK = ~CLK; //toggle clk every 5 time units ////////////////////////////////////////////////////////////////////////////////

initial begin // Initialize Inputs RESET = 1; S_parameter = 8'b00001100; #100;

RESET = 0; S_parameter = 8'b00001100; #100; end endmodule

It seems to me that it is correct but if you note something wrong let me know