Field-Programmable Gate Arrays

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xilinx virtex 2 multimedia board ( XC2V2000)

Hi I am a student and trying my hands off xilinx virtex 2 multimedia board. I was trying to run an example "Character M...
0 comments posted 21yrs
posted by manmeetbhangu
0 comments posted 21yrs posted by manmeetbhangu

[XST] FSM extraction question

Hey, I made a FSM with about 23 states (not the first time i've done vhdl work, but never had this problem before with...
4 comments posted 21yrs
posted by tim.verstraete
4 comments posted 21yrs posted by tim.verstraete

ML361 Documentation....

Hi All, I am developing a board using XC2VP20-6FF1152 with a 184 ddr pc3200. The documentation (Scheamtics and gerber/p...
2 comments posted 21yrs
posted by henrique.portela
2 comments posted 21yrs posted by henrique.portela

burn xcf16p through PCI jtag

Hi, I developed PCI board with xilinx prom & fpga on it. Since PCI has jtag pins and since the prom xcf16p is programme...
0 comments posted 21yrs
posted by nahum_barnea
0 comments posted 21yrs posted by nahum_barnea

pll

Can somebody help me wid a PLL generation code with Quartus-2 apex devices... please send me the code for that. it is ur...
0 comments posted 21yrs
posted by vryaag
0 comments posted 21yrs posted by vryaag

RocketIO code example

I'm just starting out using RIO on VII Pro devices and I need some simple VHDL to get started. There are some code snip...
2 comments posted 21yrs
posted by enquiries
2 comments posted 21yrs posted by enquiries

ISE7.1 SP4: proble and chipscope problem

Hey, Do some of you also have a problem with adding probes in fpga editor and then generating the bit file? i have the...
1 comments posted 21yrs
posted by tim.verstraete
1 comments posted 21yrs posted by tim.verstraete

chipscope/core implementation

Hi, I'm experimenting lately with an Virtex2Pro Eval Board and wit chipscope. But I'm occuring some basic problems. The...
0 comments posted 21yrs
posted by Gardovan
0 comments posted 21yrs posted by Gardovan

ISE 64bit question

XST 7.1i says that it has support for redhat linux enterprise 64 bit edition. I installed enterprise 3 on a system we h...
3 comments posted 21yrs
posted by maplante
3 comments posted 21yrs posted by maplante

used boards? cache design? DDR2 controller?

Hi all, Very new here, but not new to FPGA A few questions Does anyone know where to get cheap (used) Xilinx developmen...
0 comments posted 21yrs
posted by taebow
0 comments posted 21yrs posted by taebow

Help finding Signetics Datasheets

You FPGA guys were so nice to me when I asked questions about decapping ICs and reverse engineering PALS...I have one m...
1 comments posted 21yrs
posted by grant
1 comments posted 21yrs posted by grant

OpenTech open source designs and tools

Hello, The new release (1.5.1) of OpenTech is available now with more and more new free open source hardware designs an...
0 comments posted 21yrs
posted by jamilkhatib75
0 comments posted 21yrs posted by jamilkhatib75

to use flash on the fpga board

Hi All, Now I am using Virtex-II Pro50 Memec Design FPGA to do my projects. I want to use flash to store my data, so I...
2 comments posted 21yrs
posted by lnzhao
2 comments posted 21yrs posted by lnzhao

Signed addition

Hi I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how to define a signed number? I've the follo...
8 comments posted 21yrs
posted by rb
8 comments posted 21yrs posted by rb