implementing the tristate bus

Sep 09, 2005 3 Replies
S

Hello Guys,



I am having an IP which has 2 interface master and slave interface but there single external bus. To adapt to this architecture i using an trisatate implementation of bus. But the problem is that once i have the tristating of bus , signal interfacing to slave interface of IP gets grounded. I have observed it in chipscope (probing the EDF) but if i donot have tristating the IP is working fine. I tried all ways but still i could not solve the problem.



I will explain one of the signal interface: HTRANS



Global external bus signal is HTRANS. This signal connect directly to slave HTRANS since its a input and there is iHTRANSOut signal in master part which is output and i have this to connect to same external HTRANS.



Code goes this way:



always @(posedge iHCLKBUF) begin if (nSYSRST == 1'b0) AHBMasterEnable


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V

Williams,

From what you explain about the implementation of a tri-state, and from what I see in your code, there is no problem with both. If you cannot spot this problem in simulation, try checking hardware for any other devices driving this bus, especially if you are in the first steps of ... Any details?

Vladislav

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S

Hello Vladislav,

Thanks for the reply.

Yes i also think my implementation is correct. I have ported it to FPGA and i am facing the same problem. I am able to read the internal register (reset value) in only slave interface but if i trisatate the bus for interfacing the master and slave i reading all zeros. After probing the internal signal through chipscope i came to know that all the signal which i am tristating is being connected to ground. I am using synplify for synthesis and then EDF being implemented on ISE.

Thanks and regards williams

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V

Please go through the topic "Disconnect the FPGA I/O pads from the outside world". I think our problem is similar.

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