Field-Programmable Gate Arrays

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very urgent

hai, i need to know how to display different colour bars in vga monitor by interfacing with cpld . i need to use vhdl co...
5 comments posted 21yrs
posted by periyanayaki
5 comments posted 21yrs posted by periyanayaki

Preloading SDRAM?

Hi, I have to initialise an SDRAM with an LUT (48MB). I have the LUT in .dat format. Is there anyway I can do this with...
7 comments posted 21yrs
posted by subhasri.krishnan
7 comments posted 21yrs posted by subhasri.krishnan

CPLD program editing

Hi Group, I need to edit a program loaded in a CPLD.I can read a JDEC file from the CPLD.How can I convert that file int...
2 comments posted 21yrs
posted by akashya
2 comments posted 21yrs posted by akashya

Altera SOPC testbenching in Modelsim?

To all, I'm generating an SOPC design in Quartus using the builder and have created a custom master, slave and used a s...
0 comments posted 21yrs
posted by pinod01
0 comments posted 21yrs posted by pinod01

... failed to route using a CLK template

Hi, when using Xilinx par 7.1.03i and implementing some logic on a Xilinx XC31000, I get a warning regarding the routin...
1 comments posted 21yrs
posted by nospam.eric
1 comments posted 21yrs posted by nospam.eric

Using LogicCORE on development board with Web ISE

Hi all, I might be getting a Xilinx development board soon. I downloaded the free Web ISE toolkit from Xilinx. I am con...
4 comments posted 21yrs
posted by gh_hardy
4 comments posted 21yrs posted by gh_hardy

Turion 64 performance

Hallo, I would buy a notebook. But I'm not sure about the model. I have seen some "desktop replacements" from my colleg...
0 comments posted 21yrs
posted by marcotoschi
0 comments posted 21yrs posted by marcotoschi

newbie questions: Xilinx vs. Altera tools and parts

These questions have probabaly been asked several times but here goes. I have a software background and want to learn F...
1 comments posted 21yrs
posted by unicwkNOSPAM
1 comments posted 21yrs posted by unicwkNOSPAM

help needed

Hi all can anybody provide me the information about paralle FIR filte structures or any useful links my e-mail ID : snip...
0 comments posted 21yrs
posted by luck4you
0 comments posted 21yrs posted by luck4you

Req to Xilinx: eCos port for Microblaze

Dear Xilinx, Would you **please** consider investing money/effort into an eCos port to Microblaze? Altera has sponsored...
2 comments posted 21yrs
posted by r_fpga_dev
2 comments posted 21yrs posted by r_fpga_dev

Pricing for V2-Pro / V4-FX ?

Hi, Just wondering if someone can give me a ballpark/estimate pricing of the V2-Pro / V4-FX devices compared with a Spa...
0 comments posted 21yrs
posted by r_fpga_dev
0 comments posted 21yrs posted by r_fpga_dev

Using 3rd Party FPGA flows and Xilinx

I am new to FPGA design and have a basic question regarding using 3rd party tools with Xilinx devices. I know that ISE...
1 comments posted 21yrs
posted by chris
1 comments posted 21yrs posted by chris