Latest threads in Field-Programmable Gate Arrays

High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz

>From its datasheet, Spartan3 DCM can double clock rate up to 334MHz, ie, CLKIN can be up to 167MHz. Hence I hope that...

6 20yrs

wpora

6 20yrs wpora

There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?

Hi, I would like to kown if is possible to instatiates a N number of a specific component using a struture as "for gene...

3 20yrs

ivans

3 20yrs ivans

Preloading SDRAM?

Hi, I have to initialise an SDRAM with an LUT (48MB). I have the LUT in .dat format. Is there anyway I can do this with...

7 20yrs

subhasri.krishnan

7 20yrs subhasri.krishnan

CPLD program editing

Hi Group, I need to edit a program loaded in a CPLD.I can read a JDEC file from the CPLD.How can I convert that file int...

2 20yrs

akashya

2 20yrs akashya

Altera SOPC testbenching in Modelsim?

To all, I'm generating an SOPC design in Quartus using the builder and have created a custom master, slave and used a s...

0 20yrs

pinod01

0 20yrs pinod01

Synchronous & Asymchrnous Flip Flop Implementation

Hi All, I'm interested in how a D flip flop can be made such that the Set and Reset signals can be configured as either...

3 20yrs

ajg112

3 20yrs ajg112

... failed to route using a CLK template

Hi, when using Xilinx par 7.1.03i and implementing some logic on a Xilinx XC31000, I get a warning regarding the routin...

1 20yrs

nospam.eric

1 20yrs nospam.eric

Using LogicCORE on development board with Web ISE

Hi all, I might be getting a Xilinx development board soon. I downloaded the free Web ISE toolkit from Xilinx. I am con...

4 20yrs

gh_hardy

4 20yrs gh_hardy

Turion 64 performance

Hallo, I would buy a notebook. But I'm not sure about the model. I have seen some "desktop replacements" from my colleg...

0 20yrs

marcotoschi

0 20yrs marcotoschi

newbie questions: Xilinx vs. Altera tools and parts

These questions have probabaly been asked several times but here goes. I have a software background and want to learn F...

1 20yrs

unicwkNOSPAM

1 20yrs unicwkNOSPAM

help needed

Hi all can anybody provide me the information about paralle FIR filte structures or any useful links my e-mail ID : snip...

0 20yrs

luck4you

0 20yrs luck4you

Req to Xilinx: eCos port for Microblaze

Dear Xilinx, Would you **please** consider investing money/effort into an eCos port to Microblaze? Altera has sponsored...

2 20yrs

r_fpga_dev

2 20yrs r_fpga_dev

Pricing for V2-Pro / V4-FX ?

Hi, Just wondering if someone can give me a ballpark/estimate pricing of the V2-Pro / V4-FX devices compared with a Spa...

0 20yrs

r_fpga_dev

0 20yrs r_fpga_dev

Using 3rd Party FPGA flows and Xilinx

I am new to FPGA design and have a basic question regarding using 3rd party tools with Xilinx devices. I know that ISE...

1 20yrs

chris

1 20yrs chris

FPGA : Decimation Filter

Hi I want to implement a 32 tap decimation filter in xilinx with reloadable coefficients. I would like to get a decimat...

4 20yrs

pbijoy

4 20yrs pbijoy

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