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Synchronous & Asymchrnous Flip Flop Implementation

Hi All,

I'm interested in how a D flip flop can be made such that the Set and Reset signals can be configured as either synchronous or asynchronous.

Does anyone have any ideas how Xilinx implement their async/sync CLB flip flops?

Do they use asynchronous flips flops with a wrapper of logic so that the set and reset signals can be 'made' synchronous? (The only solution I've come up with so far).

Or is there some lower level flip-flop design that allows a switch between sync and async set and reset?

BTW, this is for an ASIC implementation, rather than an FPGA design.

Anyone any ideas? Thanks Andy

--
Dr. Andrew Greensted      Department of Electronics
Bio-Inspired Engineering  University of York, YO10 5DD, UK

Tel: +44(0)1904 432379    Mailto: ajg112@ohm.york.ac.uk
Fax: +44(0)1904 433224    Web: www.bioinspired.com/users/ajg112
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Andrew Greensted
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Andrew Greensted schrieb:

Basically for any flip-flop with synchronous reset you can add one or two pull down transistors at the right place to add asynchronous reset. The resulting flip-flop now has both reset options and you configure it by connecting the reset signal to either.

A few ways to do that are shown in detail in Xilinx patent US000006501315B1.

Kolja Sulimma

Kolja Sulimma

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sulimma

For many FPGAs the async reset is built-in to the base flop while sync reset is synthesized from the logic cell resources. Synthesis will also tie off any unused async inputs.

-- Mike Treseler

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Mike Treseler

Thanks for the tip. For anyone else who stumbles across this thread and is interested, the patent can viewed at:

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You need to search for patent number: 6501315

Reply to
Andrew Greensted

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