Hi, I have to initialise an SDRAM with an LUT (48MB). I have the LUT in .dat format. Is there anyway I can do this with the Xilinx ISE tool? I can do writes continuously but I'd like to know how to access the file in the first place. I read somewhere that I need a different IDE for it..that too only for RAM blocks. what does that mean?
I am new to this field so if this question has been asked before please do point me in the right direction (I've done a good search already).
Thanks
I think you're confusing build-time and run-time tools. ISE lets you build your FPGA project into code that can be loaded in the FPGA including any internal (distributed or block RAM) memory initialization.
External memory needs to be loaded at run time by the FPGA. File access for this depends on how your system is connected to the computer containing the file. There are probably tools for this if you're using one of the development boards and the embedded processor design kit. Perhaps this (EDK) is the "different IDE" you're referring to?
Yes I understand that the external memory needs to loaded through the FPGA. I am not using any development boards but I am using a chip that has been designed to work as a special purpose processor. I was wondering on how to access the 48MB data and convert it into bitstream to be loaded into the FPGA through the JTAG port. Please do suggest some way I can do this.
I know that Xilinx has a SystemACE format for tasks such as this, but it may require you to use an embedded processor. It is impossible, though, to convert your LUT data into a bitstream as the FPGA can't store that much data.
Subhasri krishnan schrieb:
Hi, I see two possible solutions to your problem:
1) if the Data can be calculated (e.g. a sine-table) then the algorithm can be placed in the fpga and calculate the SDRAM contents once before the rest of the system starts.2)Use a Flash memory (on board, or SD-Card, MMC-Card etc.) where your data is stored. Transfer this data to the SDRAM by some FPGA_logic before the rest of your system starts.
It is most unlikely to put this ammount of data into a bitfile, but like Stephen Craven posted before, there is a system ACE chip that supports the second solution, so your own effort will be minimized. This chip is intended as a booting solution for operating systems (e.g. to load a linux kernel after FPGA-configuration)
have a nice synthesis
Eilert
..but the data could be combined into whatever storage device is supplying the FPGA bitstream, then accessed by the FPGA once configured. SystemAce or parallel flash would seem appropriate for this amount of data.
"Subhasri krishnan" schrieb im Newsbeitrag news: snipped-for-privacy@z14g2000cwz.googlegroups.com...
they have an application that preloads an SDRAM connected to FPGA with binary image. That sdram content can be later used by the FPGA real application that needs it, the SDRAM goes into self refresh and maintains its content when CLK is stopped. Xess has I think all source code needed for this kind of applciatio available for downloads
Antti
This should be possible with XMD (a Xilinx-Tool). At least I've seen a JPEG-example uploading the jpeg to sdram by issueing a few commands in a gui-wrapped terminal (iirc XMD).
Perhaps this may help you, if not I could ask the one showing me this jpeg-example for detailed information.
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