Hi all,
I might be getting a Xilinx development board soon. I downloaded the free Web ISE toolkit from Xilinx. I am considering puting Xilinx's LogicCORE PCI IP core into it. I'm very new to this. So I'm looking for advice from the community.
Will this LogicCORE come as a particular file that I can drop into my design? I would be writing the rest of my design in verilog. I presume the LogicCORE would not be in verilog but some pregenerated block that I can add in. I presume I would synthesize my verilog and then before the PAR stage, I would need to place this pregenerated block in order to get the final bit file. Is this correct?
I'm trying to understand the various manuals but it's confusing. They talk about using a CORE Generator IP Update, manual installation and directly downloading. I think the first two are relevant to me but I don't see CORE Generator in Web ISE. Is this something that's feasible with Web ISE or would I need to purchase the full ISE?
Thanks! GHH