... failed to route using a CLK template

Sep 29, 2005 1 Replies
N

Hi,



when using Xilinx par 7.1.03i and implementing some logic on a Xilinx XC31000, I get a warning regarding the routing of my main clock that I don't understand. Could someone give an explaination as well as a way to avoid it?



WARNING:Route - CLK Net:s_clk_120MHz may have excessive skew because 5858 CLK pins failed to route using a CLK template.



Many thanks, Eric.



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M

Somehow the software has decided that either

  • your clock net does not fit on a global net (have you used all of those up) * cannot use the CLK routing methods it has built-in for doing low-skew without using global resources. One way of getting this is to apply USE_LOWSKEWLINES or MAXSKEW= constraints to a net. If the SW can figure it's a clock, it's better off left to it's own devices.

Either of those ideas help?

Cheers, MArtin

martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt
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