High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz

1. You should use the DCM in High frequency mode
2. Test if you have a Silicon revision subject to the problems listed as Spartan 3 errata by Xilinx

"wanch" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

we can only confirm that we have never seen higher than 275MHz from DCM output in S3. that correlates with your measurements. I dont think the PCB is the issue. issue is in silicon.

Antti

1. Clock doubling is only available in Low frequency Mode.
2. Tested, no such errors could be related to the problem.

Could you suggest some devices which are suitable to run at a clock rate more than 311MHz?

My Xilinx Spartan-3 Starter Kit, with -ES silicon, has exhibited similar DCM problems whenever the design uses the SRAM I/O pins.

Pin count/slew/drive settings for the SRAM buses are well within the published SSO limits for the part, but the DCM's on the left side of the chip unlock once the SRAM lines ( mostly on the left side ) start toggling.

Changing the DCM update attribute to FFFF, changing the 2x DCM feedback to CLK0, and switching to CLKFX instead of CLK2X all failed to eliminate the problem.

The only thing that helped was LOC'ing the DCM's to the right side of the chip:

attribute loc : string ; attribute loc of DCM1 : label is "DCM_X1Y0"; attribute loc of DCM2 : label is "DCM_X1Y1";

Also, check out Answer Record 19827 and the S3 errata.

Brian

"wanch" schrieb im Newsbeitrag news: snipped-for-privacy@g47g2000cwa.googlegroups.com...

well my comment was only regarding the DCM max output on slowest S3 (-ES !) I guess that fastest speed grade non -ES S3 parts go above 275MHz as DCM output.

as of actual measurement I have measured in S3 -4 silicon internal signals above 400MHz somewhere above 450MHz the fabric stops toggling

but if you manage to feed in the 311 MHz clock then the S3 fabric should still work if the design is properly done

as of other parts that run at rate of more then 311MHz out of curiosity I tested slowest speed grade Lattice EC FPGA (LFEC3E-3)

PLL input 100MHz (from LVDS oscillator) PLL output 325MHz, good signal measured on output pin PLL output 400MHz, looks like working also but as my 500MHz DSO is sampling only 1000GS/s (I dont know how to force the 2GS/s mode!) shows not so nice sinus as there arent much samples. But I think the signals is really 400MHz.

so in any case the Lattice part (cheapest, slowest) is working as of the PLL output above 311MHz at least.

Antti