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There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?

Hi, I would like to kown if is possible to instatiates a N number of a specific component using a struture as "for generate" or another one. What I'm looking for is a code with a generic number of a especific component. I want to write a peace of a repetitive text using a structure like "for loop" or "for generate" and use the number of ' N ' as an parameter to the compiler.

Supose the signals and the component above: ... clkin,input : std_logic_vector(N-1 DOWNTO 0); clkout,output : std_logic_vector(N-1 DOWNTO 0); ... component fifo port( ckwrite,din : in std_logic; ckread,dout : out std_logic); end component; ...

There is a way to instantiate 'N' VHDL components using a repetitive strutucture like this?

... for i range 0 to N-1generate

fifo_inst(i) : fifo port( ckwrite => clkin(i), din => input(i), ckread => clkout(i), dout => output(i));

end generate; ...

Thanks

Ivan

Reply to
ivan
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Umm, yeah, pretty much exactly like you've done it (snipped)! :O

Regards, Mark

Reply to
Mark McDougall

Hi Ivan, as you already showed, generate does the trick of multiple instantiations of a given component.

To do this N times you can specify a generic in your entity like this:

entity fifo_chain generic( N : integer := 8); -- 8 as a default (not neccessary) port ..... end entity; Please have a look for the correct syntax.

It is not neccessary always to edit the default in the entity. There are smarter ways. During Simulation you can change N from the configuration. Or it can be changed from the disign that instantiates the fifo_chain as a component. Maybe it is also possible to define N as a constant in a package. That could be useful if you want to create variants of a certan design. Then each variant would be syntesized with its own package and that's all to edit.

Have a nice synthesis Eilert

ivan schrieb:

--snip

Reply to
backhus

A slightly nicer way is to pass arrays around... My personal favourite

the entity has something like .... generic max_chan_g: integer := 1 -- you can override this

then the ports data_in: std_logic_vector(max_chan_g-1 downto 0)

then in the architecture

data_ff: for i in data_i'range generate -- some code end generate;

this way you get one reference.. and it cascades nicely and automatically expands and contracts as required.

Normally I will have a constant max_chan_c: integer := 4; in a header file somewhere so when you place the component in a VHDL file you simply put max_chan_g => max_chan_c in the generic section.

This method will allow portability without having to have allot of headers

Simon

Reply to
Simon Peacock

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