Latest threads in Field-Programmable Gate Arrays

Xilinx ML403 Board Beginner

Hello Group, I just received the Xilinx ML403 development kit. Wow what a board ! I especially like the high speed SMA(...

5 21yrs

bradsmallridge

5 21yrs bradsmallridge

Anyone remember the really early Xilinx FPGAs?

Hi all, I'm trying to put together a picture of how Xilinx FPGAs evolved, from the XC2000 series up to the latest Virte...

17 21yrs

almost_rational

17 21yrs almost_rational

Xilinx EDK : mb-gcc linker errors with C++ features

I am using Xilinx EDK 7.1.2 Build EDK_H.12.5.1+0, targeting the Microblaze. If I define a pure virtual function in a C+...

0 21yrs

gordonrwhite

0 21yrs gordonrwhite

Storing a file onto FPGA

Hi, I am writing a verilog code whereby I read data from a txt file and use it in one of the modules. I want to store t...

24 21yrs

robertsolanki

24 21yrs robertsolanki

IO interface standard of fpga

Who can tell me where I can find the introductions to the IO interface standard of fpga(For example,LV TTL,LV CMOS,GTL,G...

1 21yrs

zqhpnp

1 21yrs zqhpnp

Data width change in opencores Ethernet MAC

Hello, Just wondering if anyone can let me know if I'm going about this the right way - I'm trying to implement the ope...

1 21yrs

pei

1 21yrs pei

Simulink to hdl conversion

Any body please suggest any good tool to convert simulink model to equivalent RTL.

4 21yrs

vssumesh_asic

4 21yrs vssumesh_asic

IOs on ML-310 Evaluation Board

Currently, we purchased a Xilinx ML-310 Evaluation Board. The board comes with two Personality Module (PM) interfaces o...

0 21yrs

hagus

0 21yrs hagus

RAMB16 primitive write/read collision differences betweem virtex2 and virtex4

Hello, I have a design in a Virtex2 that uses RAMB16 primitives. In this design I access to this memory to write and re...

7 21yrs

jcastillo

7 21yrs jcastillo

IDELAYCTRL floorplanner/fpga editor/pace problem

Hey, I'm building a DDR2 controller and have 3 banks on a virtex 4 so 6 IDELAYCTRL blocks ... so i look in pace to loc...

2 21yrs

tim.verstraete

2 21yrs tim.verstraete

NgdBuild:455, Ngd:Build:924 when using MGT XBERT

I am currently trying to use the MGT XBERT system with an unsupported board. I have no problem synthesing the design bu...

0 21yrs

do_not_bend_42

0 21yrs do_not_bend_42

User Library in ISE

Hi all, I'd like ask you for any hint in user library creation in Xilinx ISE 7.0 (XST). I want to build my own library...

0 21yrs

xipn

0 21yrs xipn

how to implement 8x8 circular shifter on FPGA

Hi, I need to implement an 8x8 circular shifter module where I have 8 input ports (each 4 bits) that needs to be connec...

3 21yrs

ecavus

3 21yrs ecavus

Question regarding FPGA startup ROMs

Hi, I've been working with Xilinx CPLDs (mostly 95108) for quite some time now, and as my designs became more complex,...

4 21yrs

Immo.Birnbaum

4 21yrs Immo.Birnbaum

stratix fpga pll

hi all dears i am new to altera stratix fpga i want to know more about plls in the altera FPGA and how can produce a clo...

1 21yrs

sambad_20

1 21yrs sambad_20

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