NgdBuild:455, Ngd:Build:924 when using MGT XBERT

I am currently trying to use the MGT XBERT system with an unsupported board. I have no problem synthesing the design but when I try to implement the design I get the two error messages below.

Does anyone have any ideas what the problem could be? I am using only Xilinx'x own files so there shouldn't be a problem with the code. I don't really know where to start...

Rosemary

ERROR:NgdBuild:455 - logical net 'N1' has multiple driver(s): pin G on block XST_GND with type GND, pin PAD on block flib/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/N1 with type PAD

ERROR:NgdBuild:924 - input pad net 'N1' is driving non-buffer primitives: pin G on block XST_GND with type GND, pin I0 on block flib/clk_startup_0/clk_startup_0/jtgtdoen1 with type LUT2, pin I1 on block flib/clk_startup_0/clk_startup_0/jtgtdoen1 with type LUT2, pin PRE on block flib/clk_startup_0/clk_startup_0/por_ff_1 with type FDP, pin PRE on block flib/clk_startup_0/clk_startup_0/por_ff_0 with type FDP, pin PRE on block flib/clk_startup_0/clk_startup_0/por_ff_2 with type FDP, pin PRE on block flib/clk_startup_0/clk_startup_0/por_ff_3 with type FDP, pin I2 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01111 with type LUT3, pin I2 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01141 with type LUT3, pin I2 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01171 with type LUT3, pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01451 with type LUT3, pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01421 with type LUT3, pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n00991 with type LUT3, pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01021 with type LUT3, pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01051 with type LUT3, pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01081 with type LUT3, pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01111 with type LUT3, pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01141 with type LUT3, pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01171 with type LUT3, pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01191 with type LUT2

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