how to implement 8x8 circular shifter on FPGA

Use 8 X (8 channel 4 bit muxes) and drive the 3 bit addresses via a set of adders each offset by one, ignoring overflows.

By inputting the number of shifts to the front end add, the correct shifts are applied to the remaining.

Assuming your clock rate is

Enver, Depending on your device resources, you might build a barrel shifter with a multiplier. This was described in

Pip

you could use muxes or multipliers as suggested, however a lower cost solution is to use a set of layered 2:1 muxes. You'd have 4 instances, one for each bit, so let's just focus on one instance. The one bit instance consists of 3 layers of 2:1 muxes. The first layer either passes the data in the same order or rotates it by 4 positions, and is controlled by the msb of your shift control. The second layer either passes the output of the first layer unchanged or rotates it by 2 positions. The final layer passes the second layer output unchanged or rotates it by 1 position. The result takes 24 2:1 muxes per bit arranged in 3 layers of logic. If you can afford the pipeline latency, you can register each 2:1 mux for a 3 clock latency, and this will run at close to the max toggle rate of the FPGA.

If you did it with 8:1 muxes, which each consist of 7 2:1 muxes, you'd need 8 8:1 muxes, or a total of 56 2:1 muxes per bit. Using the dedicated F5 and F6 muxes in Virtex would reduce the size of the 8:1 mux, but at the cost of increased routing complexity and higher fan-out loading on the circuit driving the shifter.