Storing a file onto FPGA

Unfortunately, you're going to have to do some work. Either you have to initialize the contents of a ram (bram or lut ram) with your data, which can be done through CoreGen after you massage the txt file into an acceptable format, or you can create a microprocessor-based system using the EDK and load your txt file into a program or into the Xilinx filesystem.

I am curious about your application, though. How are you using the text file?

Thanks for the reply.

The txt file I am planning to use contains some video packets, which are generated by a set of Python scripts. Writing verilog modules to generate the data in the txt file would be to start all over again, which I think is unnecessary. I was hoping that there would be some short cut way by which you can initialize the memory on the FPGA or may be define the memory on FPGA.

How do people store long look up tables on FPGA? Especially if the look-up table data... let's say coefficients for something... are generated by some other program.

You could declare the text as a string constant in VHDL, then write a vhdl function to convert the text into the bit vector data needed to initialize the BRAM. I do a similar thing for some of the tables in my DSP design, where I generate the table and convert it to integers using Excel, then cut and paste the column from Excel into a VHDL integer array constant. The cut an paste for an integer array is easier if you put a column of commas in the column to the right of the column of integers in the excel spread sheet, and then copy both those columns to the VHDL. Likewise, you can also use matlab to generate a table of integers, writing it to a file using DLMwrite, and then opening that file with a text editor and cutting and pasting into your vhdl editor.

In the case of the string, you'll have to write your own function to convert the string characters to integers if you do it in VHDL because the synthesis tools do not recognize the textio package. It isn't hard, just tedious.

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--Ray Andraka, P.E.
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^Thanks! However, I am not much familiar with VHDL coding. Can you paste a sample verilog code?

Also, when you say cutting and pasting into VHDL code, do you mean that I'll have to do this each time the data in my txt file changes? The data I generate in the text file will change depending on my inputs. I need a way so that I can quickly load/initialize the RAM with the new values from txt file.

I can write the MATLAB code to generate the format required for initializing the RAM, but how do I actually initialize it?

Thanks in advance. Robert.

Hi Robert, your first idea appears often in a designers mind, because it works so well in simulation. But in synthesis the tool is not executing your code, only analyzing it and looking for synthesizable parts. The rest of the code will be ignored in the best case or gives you errors and warnings.

If you want to develop FPGAs with certain RAM contents defined by some other tool before synthesis you better try this flow:

- develop your design assuming that your RAM/ROM contents are available after startup.

- after PAR extract the paths to your memeory elements e.g. by using the floorplanner tool (maybe there are other ways too).

- write a BMM file (even if XILINX still makes a big secret of the syntax. :-) Read some examples, that helps.)

- use the data2mem tool to patch your bitstreams with the actual memory contents generated by your special tool or script (provide the correct file format for data2mem)

For Simulation, if you are using modelsim 6.xx, you can work similar to the above flow.

-Load your design and your testbench into vsim.

- use the mem load command to initialize the memory elements in your design (you can find out about the correct file syntax by filling some pattern directly into your memory with mem load and then storing it with mem save)

This way you don't need to use your HDLs file io anymore inside your design and have similar flows for synthesis and simulation.

have a nice synthesis Eilert

Robert wrote: >I am writing a verilog code whereby I read data from a txt file and use >it in one of the modules. I want to store the data from the .txt file >on to FPGA, where it can be used by other modules.

The answer to this would typically be yes.

I'm confused by this. In your earlier post, you said that the text file was created by a Python program. You then wanted a way to take this text, and encode it somehow and have it included in the bitstream that configures the FPGA. There are many ways to do this, and some have been described by other posters to your question.

By "inputs" do you mean signals to your FPGA, or parameters to your Python program?

If there is a small set of inputs, then I guess you could build them all and load them all into the FPGA (needs N x memory), and select at runtime what you need. If the parameters are unbounded, then you need a more complex process, since this implies running Python for each change in the inputs.

Ray pointed out that a cut-and-paste process can be used to get from a text file to a block of VHDL/Verilog initializer statements, or with Xilinx's data2mem program. If you find yourself going down this path, I highly recommend that use an editor program that includes a "column edit" mode, and maybe also a hex mode. My favorite editor is UltraEdit, that is reasonably cheap, and an excellent programmer's editor.

Philip

Philip Freidin Fliptronics

^Thanks Philip and Eilhert.

A clarification for Philip: I need to generate different data files using Python scipts and then want to store this on the FPGA. The inputs I was talking about was for the python, which will generate different output data files each time. I am not sure if it would be possible to store all of the possible data file outputs from Python onto the FPGA. Consequently, cut-paste won't be a very good option here.

For general audience:

I just found out there in Altera, its possible to define your data into a very simple memory format (addresses and data). This file can then be used to intialize the RAM/ROM on to the FPGA.

I am quite sure it can be done on Xilinx as well. But I am don't know how to do it. Can somebody show steps as to how to initialize the memory? Obviously, sample codes are not that easy to find.

Robert.

Hi Robert, Yeah, as Philip and Eilhert said, it looks like you want to use the data2mem program. This puts the data from a simple format .mem text file into your fully placed and routed Xilinx configuration bit file. This way you don't need to do a P&R every time you change the data. It's all in the documentation with examples IIRC. HTH, Syms.

If this is something you are going to be changing several times, it might not be unreasonable to write a translator that takes your text input and outputs a VHDL package containing the memory contents as a constant array. I've done that both in 'C" and in Matlab, as well as in non-synthesizable VHDL. The file containing the package just gets included with the rest of the files at design time. That way, you don't have to touch any of your design files, just one file containing a package that has your data in it. You can also generate the data file in the Xilinx .coe file format and load the data into the memories at compile time.

Hi Ray, So, why isn't it better to use 'C'/'Matlab'/Perl to generate a .mem file that data2mem loads into the previously compiled .bit file? It still meets the 'you don't have to touch any of your design files' criterion, but saves a P&R each time you change the memory contents. Cheers, Syms.

If you need to simulate the design with the block ram initialized data2mem will not help. Any given project may benefit from one, or at different times in the life cycle, both approaches.

Regards, Erik.

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It depends on your application, but if you need to simulate the design with the data in the memories (as is usually the case if the data is tables for DSP functions), data2mem is of no help. Data2mem is also one more tool that has to be run on the design, which I've had trouble with customers remembering to do if they go back and modify the design. The point is, there are many ways to do this, and what is best really depends on your situation.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Actually the synthesis tools execute some of your code: Expressions are evalutated, for and generate loops unrolled, etc. In principle there is nothing that prevents the synthesis tools to execute processes that are only activated once to determine the result.

Also, logic that converts text to integers can be described by an rtl netlist and with a little luck redundancy removal will boil it down to a lookup table. Opening files can be handled similar to an "include" statement.

But this will not happen before a flip-flop with enable can be written as: if rising_edge(clk) and enable='1' then .... which still is not understood by most synthesis tools.

At last years GI workshop there was a paper that used XML/XSLT to convert a load of "unsynthesisable" VHDL constructs into code that even XST considers to be synthesizable. Most of these transformations were really simple. Apparently the tool vendors settled years ago on what should be synthesizable and what shouldn't and now are too lazy to push that border.

Kolja Sulimma

Hi Erik, Ray, OK, simulation is a good reason! I was thinking about DSP apps where I tend to simulate to make sure the VHDL works, but often don't simulate the VHDL for every single different filter I design; I prefer to simulate just the DSP with Matlab or something similar. The design flow where I use data2mem is when I want to tweak the performance of a dsp filter (say) but don't need or want to wait for a P&R cycle each time. Once everything is working I do go back and paste the data directly into the VHDL so that subsequent builds don't require the data2mem thingy. So, as you both say, horses for courses!! Thanks guys, Syms.

I see a difference between execution and evaluation.

- execution is taking input values and producing outputs.

- evaluating is calculating the right connections (and logic etc.) between inputs and outputs. (There are probably more accurate definitions available)

I agree to that. As long as we are discussing the above problem of initializing RAMS/ROMS from files this would be a nice feature for the next VHDL Standard.

RTL... Please dont! I'd rather like an evaluation of a static expression (I hope I said this right) which costs no hardware. If format conversion would actually create (and use) logic elements , guess what will happen: Thousands of beginners will post questions like "I have created a bunch of counters with integers and the tool synthesizes them to a million gates..." :-)

Also: If you create actual logic for converting the contents of a file to some binary representation which will be executed at runtime of the chip how will you provide access to that file? Imagine the consequences, and if that really is what designers are asking for.

For initialisation purposes I would welcome it.

Especially cheap/free tools from chipvendors. I think Synopsys, Mentor or Cadence tools will understand it and create the right logic for every target architecture. Limiting tools to a style dependant subset may be somewhat annoying, because it affects the tool independance of the source code, but then if only full lrm-compliant synthesis tools would be allowed, could any company give them away for free. It's a matter of money her.

I confess, I don't know this paper. But have you taken a look at the synthesizable sources created by these tools (I assume they are creating VHDL as an output in the end) ? Would it really be so hard to write in that codestyle for yourself? How about the synthesized results? Synthesizable is not always identical to useable. Maybe the sources will become more elegant to read... Can you provide a link to that paper. It's an interesting topic.

In conclusion I might say that VHDL is under continuous development, which unfortunately is a very slow process.

Hi, Thanks everybody for the help.

Ok, here's what I have figured out so far which I am planning to use.

1) I will generate the data in a text file using Python scripts. 2) Will probably write another script or use Matlab to convert this to a .mem format which is readable by Xilinx. 3) Will use data2mem from command line to convert .mem file to either a .bit file or .v file. I will first try with verilog file, which I will then include into the project. The verilog file will contain the initialization for the RAM. Later on, I am planning to just use data2mem to generate .bit file, so that I can directly download it to the FPGA. (The different web-pages on Xilinx talk about .elf file, but as I don't have any code to write on the FPGA, but rather just some data, I don't know whether I should be concerned about this or not)

Now, if I understand it correctly, these are the only steps required. Is it necessary to do something about the RAM in the hardware design? Like specifying where to store, the memory design etc?

Robert.

Update:

Ok, I tried to do this. I defined a simple mem file like this:

@0000 2A

3B 4C 5D

I saved this as example.mem.

Now, I tried data2mem -bd example.mem -o v outputverilog.v

I was expecting a verilog file at the output. However, nothing happens. There is no error, but no output file either.

Any help would be appreciated.

Thanks, Robert.

You can already to this in synthesizable VHDL using functions. The difficulties come in from trying to read data from a file, and when working with real numbers. Both of these already exist in VHDL. The problem isn't a VHDL standards problem, rather it is due to the synthesis tools not recognizing the functions in stdio/textio and math_real. This is understandable since neither are synthesizable, but they could in principle be allowed in functions only for sythesizable code...ie for generation of constants. I do recall a while back that synplicity indicated that they would start allowing reals for developing constants. I don't know that it actually came to pass, as I haven't tried that in a number of years, as it is not generally recognized by simulators. If you want this capability to be supported in your tools, then let the synthesizer vendors know your wishes. This doesn't require any changes to VHDL as a language or any new constructs, just limited added support in the synthesis tools to allow file i/o and computation using reals in a limited set of circumstances (ie, in functions where the computation or file read results in constants).

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

I read this thread about initializing FPGA memory with some interest. Well over a year ago, I asked the XST developers in Grenoble to add support for File I/O during VHDL elaboration. This actually works in ISE

7.1! You can write a VHDL function that opens a file (using the TextIO package), reads data out of it, and returns an array that can be used to initialize a signal array that has memory inferred on it. You can also write files, if you feel like you have a need for it. I argued that there exists a subclass of File I/O operations that can fit into the model of constant propagations that occur during elaboration. I've used this to write a VHDL function that will read an Intel MCS file into a ram array initial value during synthesis. In principal, anything you can parse in VHDL is fair game, although in practice, I've found the file IO a little fragile, especially when dealing with access types. Read the XST documentation to see how it's done.

I have various nefarious plans for this capability, particularly in the area of automatically iterated code that refashions the circuit topology to deal with the timing failures found on the previous iteration.

Bottom line... you can read and write files during VHDL synthesis with XST. I've heard some talk about Verilog 2001 being used for much the same thing, but don't know if it works yet.

I'm not satisfied with synthesis File I/O in VHDL... I'd much rather have the ability in VHDL to control synthesis iteration on sub-components that fail to meet timing. But that's an argument I'm saving for the VHDL-200X committee.

John