Field-Programmable Gate Arrays

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How to Reduce Interconnects (VDD and VSS)

Hi.. I am using an 32MB SDRAM Unbuffered Module of Micron in m project.It has 168 pins First i got a module having 18 C...
19 comments posted 21yrs
posted by fahadislam2002
19 comments posted 21yrs posted by fahadislam2002

question: timing constraint for clock enable

Let's assume I have a global clock running at 80 MHz and a 2 bit counter running from this clock, which generates a 20...
3 comments posted 21yrs
posted by sflock
3 comments posted 21yrs posted by sflock

PCIXCAP

Assuming the desired bus speed is Conventional PCI @ 33MHz via PCI-X slot, does one have to assert and then deassert PC...
0 comments posted 21yrs
posted by shane.tietjen
0 comments posted 21yrs posted by shane.tietjen

LUT 4:1 VS FF

HI! I'm a noob here. I have to estimate and confront the area occupied by a LUT 4:1 and the area occupied by an FF. Can...
7 comments posted 21yrs
posted by lalo
7 comments posted 21yrs posted by lalo

ModelSim XE: Can't import vital 2000 library

Hi, I have a problem with ModelSim XE II 5.6a. I can't execute any simulations beyond behavioral, because ModelSim does...
1 comments posted 21yrs
posted by joerg.rockstroh
1 comments posted 21yrs posted by joerg.rockstroh

Problems with phase shift dcm

Description of the problem: I use a spartan 3-400 FPGA. A clk_100 (100 MHz), generated by a DCM is coming out of the FP...
0 comments posted 21yrs
posted by creemers_roger
0 comments posted 21yrs posted by creemers_roger

converting 12v signal to 3.3v

Hi, I would like to convert signal at 12volt to a 3.3v for connecting it to input pin of a spartan3 fpga. And then conv...
16 comments posted 21yrs
posted by KCLO4[no_spam]
16 comments posted 21yrs posted by KCLO4[no_spam]

iVerilog / VVP output to GTKwave.

Hi All. I have a test routine that successfully compiles in iVerilog. I process my verilog source as follows: /usr/loca...
3 comments posted 21yrs
posted by nospam-news
3 comments posted 21yrs posted by nospam-news

Compiling Altera LPM FIFO into Modelsim Error

To all, I have been attempting to load a lpm component into a Modelsim project and when I get my test bench compiled an...
4 comments posted 21yrs
posted by pinod01
4 comments posted 21yrs posted by pinod01

64 bit processor for FPGA workstation?

I'm still mulling over replacing my aging system. Looks like a lot of the newer workstation class processors are 64 bit...
5 comments posted 21yrs
posted by ray
5 comments posted 21yrs posted by ray

What is a "full custom" design?

Apologies for posting in an FPGA group, but I couldn't think of a more appropriate one. I hear ASIC designers talk abou...
4 comments posted 21yrs
posted by pm940
4 comments posted 21yrs posted by pm940

Xilinx Chipscope VIO Core Utilization

Dear Google Group Members, Does anyone know how to instantiate a Xilinx Chipscope Pro VIO Core? I understand that one m...
2 comments posted 21yrs
posted by happydude32905
2 comments posted 21yrs posted by happydude32905

Eliminates meta stability (yes or no)?

I new idea? What do you experts think of the following entity I wrote? It?s purpose is to eliminate metastability of th...
7 comments posted 21yrs
posted by mr
7 comments posted 21yrs posted by mr

Verilog VPI

Hi, I'm developing in verilog (Xilinx web pack with Modelsim XE). I came to the point I have to use some external c sof...
0 comments posted 21yrs
posted by slawc
0 comments posted 21yrs posted by slawc

Using the BSCAN primitives

Hello, I'm looking for some example on how to use the USER1,2 functions in a spartan 3 (examples on virtex2/4 or others...
3 comments posted 21yrs
posted by com.246tNt
3 comments posted 21yrs posted by com.246tNt