Latest threads in Field-Programmable Gate Arrays

question: timing constraint for clock enable

Let's assume I have a global clock running at 80 MHz and a 2 bit counter running from this clock, which generates a 20...

3 20yrs

sflock

3 20yrs sflock

PCIXCAP

Assuming the desired bus speed is Conventional PCI @ 33MHz via PCI-X slot, does one have to assert and then deassert PC...

0 20yrs

shane.tietjen

0 20yrs shane.tietjen

LUT 4:1 VS FF

HI! I'm a noob here. I have to estimate and confront the area occupied by a LUT 4:1 and the area occupied by an FF. Can...

7 20yrs

lalo

7 20yrs lalo

ModelSim XE: Can't import vital 2000 library

Hi, I have a problem with ModelSim XE II 5.6a. I can't execute any simulations beyond behavioral, because ModelSim does...

1 20yrs

joerg.rockstroh

1 20yrs joerg.rockstroh

Problems with phase shift dcm

Description of the problem: I use a spartan 3-400 FPGA. A clk_100 (100 MHz), generated by a DCM is coming out of the FP...

0 20yrs

creemers_roger

0 20yrs creemers_roger

converting 12v signal to 3.3v

Hi, I would like to convert signal at 12volt to a 3.3v for connecting it to input pin of a spartan3 fpga. And then conv...

16 20yrs

KCLO4[no_spam]

16 20yrs KCLO4[no_spam]

iVerilog / VVP output to GTKwave.

Hi All. I have a test routine that successfully compiles in iVerilog. I process my verilog source as follows: /usr/loca...

3 20yrs

nospam-news

3 20yrs nospam-news

Compiling Altera LPM FIFO into Modelsim Error

To all, I have been attempting to load a lpm component into a Modelsim project and when I get my test bench compiled an...

4 20yrs

pinod01

4 20yrs pinod01

64 bit processor for FPGA workstation?

I'm still mulling over replacing my aging system. Looks like a lot of the newer workstation class processors are 64 bit...

5 20yrs

ray

5 20yrs ray

What is a "full custom" design?

Apologies for posting in an FPGA group, but I couldn't think of a more appropriate one. I hear ASIC designers talk abou...

4 20yrs

pm940

4 20yrs pm940

Xilinx Chipscope VIO Core Utilization

Dear Google Group Members, Does anyone know how to instantiate a Xilinx Chipscope Pro VIO Core? I understand that one m...

2 20yrs

happydude32905

2 20yrs happydude32905

Eliminates meta stability (yes or no)?

I new idea? What do you experts think of the following entity I wrote? It?s purpose is to eliminate metastability of th...

7 20yrs

mr

7 20yrs mr

Verilog VPI

Hi, I'm developing in verilog (Xilinx web pack with Modelsim XE). I came to the point I have to use some external c sof...

0 20yrs

slawc

0 20yrs slawc

Using the BSCAN primitives

Hello, I'm looking for some example on how to use the USER1,2 functions in a spartan 3 (examples on virtex2/4 or others...

3 20yrs

com.246tNt

3 20yrs com.246tNt

Xilinx IPIF PLB Master Update

Hello All: Jsut an update on my efforts on using the Xilinx IPIF for a PLB master. Per another user's recommendation (t...

1 20yrs

emh203

1 20yrs emh203

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