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IDELAYCTRL floorplanner/fpga editor/pace problem

Hey,

I'm building a DDR2 controller and have 3 banks on a virtex 4 so 6 IDELAYCTRL blocks ... so i look in pace to loc them (as this is preferred method) and it seems that it only locks 4/6 IDELAYCTRL blocks on the right place and the other 2 not ... this is in PACE ....

When i lock it in floorplanner i get the same issue ...

When i look at it (ngd/ncd) in fpga editor they are at the right place???? who should i believe???? the strange this is that this is happening in the middle banks ... so the small banks in the middle of the fpga?? because when i loc those2 IDELAYCTRL on the other (left/right) banks i don't have that problem? is this a bug in the software?

Any help is welcome .... thanks in advance,

kind regards,

Tim

Reply to
Tim Verstraete
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Tim, What part and package are you attempting to use? It has been my observation that when xilinx has put multiple V4 parts into a common package, the parts with fewer IOs will have their NC pins located in the middle of the left and right sides. Perhaps this is the case but without more specifics, I don't think anyone will be able to assist you.

Pip

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Reply to
pipjockey

i'm using the V4SX55 - FF1148 and the banks that i want to place IDELAYCTR's are bank 6,1 and 5...

so idelayctrl_loc:

INST "DDR2_interface/i_DDR/DelayCtrl_0_b_U" LOC = "IDELAYCTRL_X0Y6" ; INST "DDR2_interface/i_DDR/DelayCtrl_1_b_U" LOC = "IDELAYCTRL_X0Y7" ; INST "DDR2_interface/i_DDR/DelayCtrl_2_b_U" LOC = "IDELAYCTRL_X1Y4" ; INST "DDR2_interface/i_DDR/DelayCtrl_3_b_U" LOC = "IDELAYCTRL_X1Y5" ; INST "DDR2_interface/i_DDR/DelayCtrl_4_b_U" LOC = "IDELAYCTRL_X2Y6" ; INST "DDR2_interface/i_DDR/DelayCtrl_5_b_U" LOC = "IDELAYCTRL_X2Y7" ;

kind regards,

Tim

Reply to
Tim Verstraete

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