Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

ml310 DDR problem

In our lab we have a number of ml310s and use them for both PPC and MicroBlaze designs. For the PPC designs using the e...
1 comments posted 20yrs
posted by scraven
1 comments posted 20yrs posted by scraven

Trying to define Opendrain Outputs

Hi, I am using Lattice FPGA EC10. I have two pins "IIC_SCL_2V" and "IIC_SDA_2V" which I want to define as opendrain out...
5 comments posted 20yrs
posted by ALuPin
5 comments posted 20yrs posted by ALuPin

Suggestions on good books

I'm looking for a good book that goes deeply into theory about transmission lines and crosstalk in high speed communica...
7 comments posted 20yrs
posted by mchan
7 comments posted 20yrs posted by mchan

UART CORE FOR NIOS

We are working on a proect using NIOS which needs to talk to the PC Via a serial port, However we found that the core s...
3 comments posted 20yrs
posted by lesnleung
3 comments posted 20yrs posted by lesnleung

Data recovery (XAPP224)

Hi all, I have a doubt in application note XAPP224. In my application the data is to be recovered at 100 Mb/s. Now my q...
2 comments posted 20yrs
posted by praveen.kantharajapura
2 comments posted 20yrs posted by praveen.kantharajapura

Cyclone II and Stratix II dual ports are dead

The innovation is not only built in, it's engineered in. I don't believe I've seen a more embarrassing issue in a long...
1 comments posted 20yrs
posted by altera_smells
1 comments posted 20yrs posted by altera_smells

ml300 LCD question

Hello, I'm Eric and I'm an undergraduate at the University of Maryland helping out with research and am very inexperien...
0 comments posted 20yrs
posted by eyeh
0 comments posted 20yrs posted by eyeh

xst synthesis

Hi, I am having problems with XST Synthesis from Xilinx. When synthesizing a unit from my created IP, the synthesis too...
4 comments posted 20yrs
posted by brassaro
4 comments posted 20yrs posted by brassaro

Lattice XP flash memory access.....

hi, does anybody know if the flash memory in these new XP devices is generally accessable from user's design? if so, ho...
2 comments posted 20yrs
posted by r.kinkead
2 comments posted 20yrs posted by r.kinkead

complexity of arithmetic

i everyone, i'm teaching a vlsi design class, and we're covering datapath this week. we use weste and harris' new editi...
3 comments posted 20yrs
posted by adnan.aziz
3 comments posted 20yrs posted by adnan.aziz

Quartus crash

Any ideas what causes (or better how to avoid) the following crash: Internal Error: Sub-system: FYGR, File: fygr_list_of...
2 comments posted 20yrs
posted by mschoebe
2 comments posted 20yrs posted by mschoebe

Raggedstone1, MINI-CAN - Low Cost Carriage

For all of you that asked if we could do better on carriage we now have a low cost option for selected EEC countries. U...
2 comments posted 20yrs
posted by removethisthenleavejea
2 comments posted 20yrs posted by removethisthenleavejea

ISE 6.2i strange behavior

Hi ! I installed ISE and EDK 6.2i with SP3, and ISE as a stange behavior. When I go through steps synthesis, P&R and .b...
3 comments posted 20yrs
posted by t
3 comments posted 20yrs posted by t

Multiple Waits 2 Xilinx WebPack???

This is problem FPGA - Virtex and proce proces begin if(i1='1') then go
2 comments posted 20yrs
posted by rulllesss
2 comments posted 20yrs posted by rulllesss