Hi all, I have a doubt in application note XAPP224. In my application the data is to be recovered at 100 Mb/s. Now my question is should i use a 100 Mhz clock only to clock the PLL, to derive CLK0 and CLK 90 OR can i use a 24 MHZ clock as a input to my PLL to derive CLK0(100 Mhz) and CLK90(100 Mhz with 90 degree) phase shift.
Regards, Prav
From a 24 MHz input, the Xilinx DCM would provide a 100 MHz output (25/6 ratio) on the CLKFX outputs, not the CLK0 and CLK90 outputs. You would need to feed your 100 MHz clock into a separate DCM to provide the phase shifts.
I think that CLK0 and CLK90 has the same frequency as the input clk Regard
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