Hi all, I have a doubt in application note XAPP224. In my application the data is to be recovered at 100 Mb/s. Now my question is should i use a 100 Mhz clock only to clock the PLL, to derive CLK0 and CLK 90 OR can i use a 24 MHZ clock as a input to my PLL to derive CLK0(100 Mhz) and CLK90(100 Mhz with 90 degree) phase shift.
Regards, Prav