Hi,
I am using Lattice FPGA EC10.
I have two pins "IIC_SCL_2V" and "IIC_SDA_2V" which I want to define as opendrain outputs so that my external processor can drive the lines to LOW.
In my VHDL top level file I define the following
ENTITY top IS PORT ( ... IIC_SCL_2V : INOUT std_logic; IIC_SDA_2V : INOUT std_logic; .... ); END top;
ARCHITECTURE struct OF top IS .=2E. BEGIN IIC_SCL_2V
I have no tristate enable signal available to define something like IIC_SCL_2V
ALuPin a =E9crit:
Yes, I know.
answer ... no you MUST have a tristate enable. If you want a repeater you will need additional hardware to detect current flow OR you can process commands for all devices and intelligently switch when you think they want to reply.
Simon
Yes, I know.
You can't permanently set scl_out to '0' -- there's your problem! If you DO set it to '0' all the time, then of course the tools go, "ah, scl_out never changes, so we can optimize all this stuff out."
scl_out is the output enable. An i2c master uses open-drain outputs for SCL (to allow a slave to insert wait states by pulling SCL down). So your internal SCL logic is really generating the output enable, and one would assume it toggles.
If you're doing an I2C slave, and this slave doesn't need to insert wait states, then you can simply make SCL an input.
-a
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