Latest threads in Field-Programmable Gate Arrays

ISE SP4 installer on Linux

Is anyone else having problems with the ISE service pack 4 installer crashing on Linux (any flavour)? SP2 worked all ri...

4 20yrs

aholtzma

4 20yrs aholtzma

Help needed regarding VPR

Hi, We need to evaluate new CLB architectures for routing area and delay. In VPR how can I specify my CLB architecture...

0 20yrs

vivekgarg330

0 20yrs vivekgarg330

3 devices on the same external bus

Hi everyone. I am designing a new board with FPGA. I have man memory devices but 3 of them (sram, flash and RTclk) will...

2 20yrs

calaf_calaf_calaf

2 20yrs calaf_calaf_calaf

Celoxica RC1000 Linux driver

Hi All, We've got a few Celoxica RC1000 FPGA boards that we'd like to use within a Linux environment. Has anyone had an...

0 20yrs

ajg112

0 20yrs ajg112

Rise time/fall time for Spartan3 clock inputs

Hi there, I am encountering a strange problem in a state machine using a 33M3333 clock in a Spartan3 FPGA. >From time t...

9 20yrs

abeaujean

9 20yrs abeaujean

Research Position

Hi Folks, I just wanted to make you aware of an open research position we have at WSI/GRIS, Tuebingen University, Germa...

2 20yrs

knittel

2 20yrs knittel

Multiple instantiation in SystemC

Hi, I have followed the design in systemC, but I have some troubles when instantiating multiples components. In bankreg...

0 20yrs

moises.paniagua

0 20yrs moises.paniagua

RoHS

I've read accounts indicating that RoHS compliance has been known to cause issues in high-speed designs. Being that FPG...

14 20yrs

0_0_0_0_

14 20yrs 0_0_0_0_

Using JTAG cable for general comms

Hello, Is it possible to use a JTAG cable connection to transfer data into and out of an FPGA during regular operations...

1 20yrs

nchandra

1 20yrs nchandra

Having trouble Detecting ethernet packets using ethereal

Hello Everyone again, This topic is troubling me for couple of weeks now. I want to get over this as quickly as possibl...

8 20yrs

achiluka

8 20yrs achiluka

64/65-octet encapsulation IP cores?

I am looking for RTL "64/65-octet encapsulation" IP core, compliant with IEEE802.3ah sec. 61.3.3. Does anyone know wher...

0 20yrs

robertem

0 20yrs robertem

Xilinx flip-chip PCB processing

Anyone here using a Virtex in a flip-chip package? If so, what precautions do you take during pcb processing to make su...

1 20yrs

asorensen

1 20yrs asorensen

Power on problem--- signal behaving strangely

Hi I am using a Spartan XC3S400 FPGA. Initially after poweron one particular signal read_enable does not get enabled. I...

1 20yrs

svasus

1 20yrs svasus

downloading with XMD ?

Hi, I'am wondering about the download capabilities of XMD. If an FPGA is configured with impact on the JTAG, then softw...

7 20yrs

t

7 20yrs t

Help needed to design recursive digital circuit

Hi all I have problem in designing a circuit which is recursive Suppose i am designing a schematic of BRLSHIFTER and su...

1 20yrs

piyushgpatel

1 20yrs piyushgpatel

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