Field-Programmable Gate Arrays

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Multiple Waits 2 Xilinx WebPack???

This is problem FPGA - Virtex and proce proces begin if(i1='1') then go
2 comments posted 20yrs
posted by rulllesss
2 comments posted 20yrs posted by rulllesss

ISE SP4 installer on Linux

Is anyone else having problems with the ISE service pack 4 installer crashing on Linux (any flavour)? SP2 worked all ri...
4 comments posted 20yrs
posted by aholtzma
4 comments posted 20yrs posted by aholtzma

Help needed regarding VPR

Hi, We need to evaluate new CLB architectures for routing area and delay. In VPR how can I specify my CLB architecture...
0 comments posted 20yrs
posted by vivekgarg330
0 comments posted 20yrs posted by vivekgarg330

3 devices on the same external bus

Hi everyone. I am designing a new board with FPGA. I have man memory devices but 3 of them (sram, flash and RTclk) will...
2 comments posted 20yrs
posted by calaf_calaf_calaf
2 comments posted 20yrs posted by calaf_calaf_calaf

Celoxica RC1000 Linux driver

Hi All, We've got a few Celoxica RC1000 FPGA boards that we'd like to use within a Linux environment. Has anyone had an...
0 comments posted 20yrs
posted by ajg112
0 comments posted 20yrs posted by ajg112

Rise time/fall time for Spartan3 clock inputs

Hi there, I am encountering a strange problem in a state machine using a 33M3333 clock in a Spartan3 FPGA. >From time t...
9 comments posted 20yrs
posted by abeaujean
9 comments posted 20yrs posted by abeaujean

Research Position

Hi Folks, I just wanted to make you aware of an open research position we have at WSI/GRIS, Tuebingen University, Germa...
2 comments posted 20yrs
posted by knittel
2 comments posted 20yrs posted by knittel

Multiple instantiation in SystemC

Hi, I have followed the design in systemC, but I have some troubles when instantiating multiples components. In bankreg...
0 comments posted 20yrs
posted by moises.paniagua
0 comments posted 20yrs posted by moises.paniagua

RoHS

I've read accounts indicating that RoHS compliance has been known to cause issues in high-speed designs. Being that FPG...
14 comments posted 20yrs
posted by 0_0_0_0_
14 comments posted 20yrs posted by 0_0_0_0_

Using JTAG cable for general comms

Hello, Is it possible to use a JTAG cable connection to transfer data into and out of an FPGA during regular operations...
1 comments posted 20yrs
posted by nchandra
1 comments posted 20yrs posted by nchandra

64/65-octet encapsulation IP cores?

I am looking for RTL "64/65-octet encapsulation" IP core, compliant with IEEE802.3ah sec. 61.3.3. Does anyone know wher...
0 comments posted 21yrs
posted by robertem
0 comments posted 21yrs posted by robertem

Xilinx flip-chip PCB processing

Anyone here using a Virtex in a flip-chip package? If so, what precautions do you take during pcb processing to make su...
1 comments posted 21yrs
posted by asorensen
1 comments posted 21yrs posted by asorensen

Power on problem--- signal behaving strangely

Hi I am using a Spartan XC3S400 FPGA. Initially after poweron one particular signal read_enable does not get enabled. I...
1 comments posted 21yrs
posted by svasus
1 comments posted 21yrs posted by svasus

downloading with XMD ?

Hi, I'am wondering about the download capabilities of XMD. If an FPGA is configured with impact on the JTAG, then softw...
7 comments posted 21yrs
posted by t
7 comments posted 21yrs posted by t