DCM corner issue

Cher Sebastien, What part are you using? Virtex4? Have you seen answer 21127? HTH, Syms.

That concerns itself with a lower than 500 MHz possible CLKIN if the device has been baked at high Vdd AND high temperature (see the NBTI white paper).

In actual fact, we saw this effect in HTOL testing with the production tester, but have never seen it in actual fact either on the test bench, or in any testing done by any customers.

There is a suspicion that the testing done is far too tough, and the problem only appears on the production tester (which tests to >700 MHz, with a +/- 100 MHz sampling) in its tests to ensure that the DCM will operate over all corners of the process, voltage and temperatures).

For any device with a DCM:

More likely is that the placement of the DCM affects the timing of the paths that are used.

Check all the constraints, and check to see that the global clock resources are bring routed properly by looking at the design in FPGA Editor.

For V2 Pro there are clock macros which are used to minimize the possible skew from different DCM locations. If this is V2 Pro, then I could see this happening if the macros were not being used.

Austin

Sym> Cher Sebastien,

Hi Austin I use an V2P70, which is loaded at 76% I don't use any macro for DCM. Which one should I use

Concerning placement and routing, all constraints have been met. It'

possible that this part is not constraint enough..

Additional information. When I use a lighter version of my desig

(which is loaded at 20%), it works.

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Aust> Hi Austin,

Thank you Austin I have to try, but the application note depicts exactly my case

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