Hi Does somebody know DCM corner issues? My DCM is not running at ver high clock rate (only 107MHz), so I don't think this issue i connected with XAPP685 application note
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This DCM is used with an DDR-SDRAM memory controller, and when I plac it at X3Y0 instead of X2Y0, memory reading often fails (data ar wrong). Thus the solution is not complicated, I just need not t use DCM X3Y0 but I would like to understand why it fails and i somebodyelse knows this problem. Thank you
21127 would not cause what Sebastien is experiencing (on V4),
That concerns itself with a lower than 500 MHz possible CLKIN if the device has been baked at high Vdd AND high temperature (see the NBTI white paper).
In actual fact, we saw this effect in HTOL testing with the production tester, but have never seen it in actual fact either on the test bench, or in any testing done by any customers.
There is a suspicion that the testing done is far too tough, and the problem only appears on the production tester (which tests to >700 MHz, with a +/- 100 MHz sampling) in its tests to ensure that the DCM will operate over all corners of the process, voltage and temperatures).
For any device with a DCM:
More likely is that the placement of the DCM affects the timing of the paths that are used.
Check all the constraints, and check to see that the global clock resources are bring routed properly by looking at the design in FPGA Editor.
For V2 Pro there are clock macros which are used to minimize the possible skew from different DCM locations. If this is V2 Pro, then I could see this happening if the macros were not being used.
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