hi, does anybody know if the flash memory in these new XP devices is generally accessable from user's design? if so, how much (spare) capacity might exist outside the bitstream and whether it could be usefully used for key storage or sections of code/data? thanks ;o)
The flash is not directly accessible by the FPGA logic (unless you route I/O pins to the config logic, which seems dangerous). You can reprogram the flash from the JTAG or serial/parallel interface with the FPGA running a previous download, because the SRAM is not automatically updated when the Flash is programmed.
For keys that don't change, you can obviously store the key in flash as register or memory initialization values. You can also directly access the flash using the parallel programming port if the I/O pins aren't needed for normal functioning. This might ease the serialization of keys for example after the bulk of the FPGA code is already loaded.
There is no indication in the user manuals that there is excess capacity in the flash beyond the bitstream.
I was hoping there *may* have been a manner to use all the flash. I'd thought that the flash memory must be oversized in typical cases - for example if in a design I specified all the the memory blocks to be ROMs (is this possible?) then their initialisation data would have to arrive in from that flash area....?however if I instead used only RAMs then that flash memory must be sitting there unused? Maybe it was just too fiddly for lattice to expose any "left over" flash memory - but even if it was a modest interface (SPI would do!) then that would be quite useful (for some designs).
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