The innovation is not only built in, it's engineered in. I don't believe I've seen a more embarrassing issue in a long time. Well, at least since ARM based Excalibur and Mercury were released to zero sales. Can't even read and write to dual port rams? That should be an automatic 100% correct feature. Better set your safe write and safe read parameters. Weren't dual port rams built into FPGAs around 10 years ago? Doh!
From: Altera Customer Notification [mailto: snipped-for-privacy@altera.com] Subject: Important Update for Stratix II and Cyclone II Devices
Dear customer,
Altera has identified M4K memory block issues affecting Stratix(R) II and Cyclone(TM) II FPGAs. Please see below for a description of the issues and links to more information.
Issue Description:
Stratix II M4K Read Issue
An intermittent read failure has been detected on Stratix II FPGA M4K memory blocks in dual clock dual port mode due to a software configuration error.
Cyclone II M4K Write Issue
A write error has been detected on Cyclone II FPGA M4K memory blocks when using dual ports and dual clocks.
Action Required:
If you are using Stratix II or Cyclone II devices, read the updated errata sheets on the Altera(R) web site.
Stratix II FPGA Family Errata Sheet:
Cyclone II FPGA Family Errata Sheet:
For further information please contact your FAE or file a service request through MySupport at:
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You are receiving this notification because you have a license to use Altera's Quartus II software, Quartus II Web Edition software, or are an Altera customer.
Please do not respond to this e-mail to get further information on this issue. This mailbox is not monitored by technical support.
Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA