Latest threads in Field-Programmable Gate Arrays

Will ISE 8.1 work together with EDK 7.1?

Any issues? -- ---------------------------------------------- Posted with NewsLeecher v3.5 Beta 2 * Binary Usenet Leech...

7 20yrs

Software- to- PCI design communication.

Hi, please guide me on two beginner-level questions. A program writes an integer onto BAR0 on the Stratix PCI board. I...

1 20yrs

mohit.tiwari

1 20yrs mohit.tiwari

Xilinx 7.1 ISE ModelSim input files

I haven't been able to use my old testbenches with the new ISE simulator. I get an error saying that the input file was...

2 20yrs

bradsmallridge

2 20yrs bradsmallridge

International Symposium on FPGAs -- Call for Participation

Please join us in sunny Monterey, California for the Fourteenth ACM/SIGDA International Symposium on Field-Programmable...

0 20yrs

guy.lemieux

0 20yrs guy.lemieux

application running on the top of Linux on virtex-ii pro

Hi All, I successfully ported Linux to the powerpc on a virtex-ii pro board. Now I'm having trouble writing sample appl...

2 20yrs

dasani8888

2 20yrs dasani8888

Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?

http://direct.xilinx.com/direct/webpack/81/WebPACK_81i_SFD.sh server maxes out at 30 kB / second (= > 7 hours)? (My DSL...

6 20yrs

pNaonStpealmtje

6 20yrs pNaonStpealmtje

Xilinx Routing & Clock/Data Skew

I am working on a timing simulation of an array of source synchronous flip-flops with all D inputs connected to the sam...

0 20yrs

billingworth

0 20yrs billingworth

Altera MAX-II: User logic access to USERCODE_REGISTER?

I would like to do something like: module maxii (..pin1,pin2..); ... output pin1; output pin2; ... assign pin1 = USERCO...

8 20yrs

newsmailcomp6

8 20yrs newsmailcomp6

FPGA configuration time for PCI identification ?

Hello, We have a 2VP40 ( 15.5Mbits configuration ) to configure through a 8 bits 90ns flash by a CPLD. I try to find wh...

8 20yrs

t

8 20yrs t

Seminar Reminder (UK)

We still have some places left at our free MicroBlaze based seminars and labs for anyone interested. 3 dates currently...

0 20yrs

removethisthenleavejea

0 20yrs removethisthenleavejea

ISE 8.1i WebPack available

Xilinx ISE 8.1i WebPack has just become available. Leon

6 20yrs

leon_heller

6 20yrs leon_heller

Breaking of Ethernet Frames

Hi All, I am very new to the Ethernet area. I am trying to design and Implement an Ethernet switch or Multiplexer. so s...

1 20yrs

kedarpapte

1 20yrs kedarpapte

want to know abt companies giving internship for 6 months

hello all, I am g.venkat ramdas doing my M.S in I2IT, pune.We are in our final sem and we are looking for project ideas...

0 20yrs

vlsipassion11

0 20yrs vlsipassion11

about the ftp.altera.com

Hi, dears: You know altera put many documents and install files on their ftp station, ftp.altera.com but can some one t...

2 20yrs

mailwz

2 20yrs mailwz

tcam implemented in fpga

Now I want a Tcam ,and the need is below,read must be completed in 1 cycle,Entry 2048,word length 32bits,If I can implem...

7 20yrs

bjzhangwn

7 20yrs bjzhangwn

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