Please join us in sunny Monterey, California for the Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays! At the conference you will learn about the latest and greats FPGA architectures, the inner workings of CAD algorithms, and novel applications for using FPGAs.
Early registration deadlines are Jan 31, but why wait?
Conference registration is available online and the preliminary program for FPGA 2006 is attached below.
We look forward to seeing you in Monterey this February!
On behalf of the Organizing Committee, Guy Lemieux Publicity Chair
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FPGA 2006 PRELIMINARY TECHNICAL PROGRAM
Synopsis
This year the conference has an exceptionally exciting program. Architecture papers consider design of a low-power 90nm FPGA, embedding floating-point units, design of clocking networks, the sustainability of defect tolerance, and a quantitative comparison of FPGAs versus ASICs. CAD papers study the optimality and performance of logic synthsis and technology mapping, design for layout, pipeline synthesis, pipelined routing, and power-aware technology mapping into RAMs. Novel applications include a cache emulator, an adaptive reed solomon decoder, an interative division algorithm, a crossbar scheduler, a unified comparison of pattern- matching circuit architectures, customized soft core processors, custom discrete Fourier tranform cores, and a secure hash function. Emerging technology papers provide a snapshot of longer-term research that promises to significantly alter FPGAs as we know them: vertically stacking multiple active CMOS transistor layers, mapping circuits to a hybrid CMOS/NANO architecture, and a non-volatile magnetic tunneling junction FPGA.
Schedule
Wednesday, February 22
6:00pm-8:00pm Registration 7:00pm-8:30pm Welcome ReceptionThursday, February 23
Session 1: Architecture 1 (Chair: Trevor Bauer)
9:00am A 90nm Low-Power FPGA for Battery-Powered Applications Tim Tuan, Sean Kao, Arif Rahman, Satyaki Das, and Steve Trimberger Xilinx Inc.Embedded Floating-Point Units in FPGAs Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, and K. Scott Hemmert University of Washington
Measuring the Gap Between FPGAs and ASICs Ian Kuon and Jonathan Rose University of Toronto
10am Poster Session 1Session 2: CAD 1 (Chair: Kia Bazargan)
11:00am Optimality Study of Logic Synthesis for LUT-Based FPGAs Jason Cong and Kirill Minkovich UCLAImprovements to Technology Mapping for LUT-Based FPGAs Alan Mishchenko, Satrajit Chatterjee, and Robert Brayton University of California, Berkeley
Improving Performance and Robustness of Domain-Specific CPLDs Mark Holland and Scott Hauck University of Washington
12pm LunchSession 3: Application 1 (Chair: John Wawrzynek)
1:30pm Design, Implementation, and Verification of Active Cache Emulator (ACE) Jumnit Hong, Eriko Nurvitadhi, and Shih-Lien Lu Intel Corp.Modeling the Data-Dependent Performance of Pattern- Matching Architectures Christopher R. Clark and David E. Schimmel Georgia Tech
An Iterative Division Algorithm for FPGAs Jianhua Liu, Michael Chang, Chung-Kuan Cheng University of California, San Diego
2:30pm Poster Session 2Session 4: Architecture 2 (Session Chair: Carl Ebeling)
3:30pm Yield Enhancements of Design-Specific FPGAs N. Campregher, P.Y.K. Cheung, G.A. Constantinides, and M. Vasilko Imperial CollegeFPGA Clock Network Architecture: Flexibility vs. Area and Power Julien Lamoureux and Steven J.E. Wilton University of British Columbia
7:00pm Evening Panel (Moderator: Mike Hutton)Friday, February 24
Session 5: Emerging Technologies (Chair: Guy Lemieux)
9:00am Performance Benefits of Monolithically Stacked 3D-FPGA Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, and Simon Wong Stanford UniversityMagnetic Tunneling Junction based FPGA Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, and Gaston Cambon LIRMM/UMII
A Reconfigurable Architecture for Hybrid CMOS/Nanodevice Circuits Dmitri B. Strukov and Konstantin K. Likharev Stony Brook University
10am Poster Session 3Session 6: Application 2 (Chair: John Lockwood)
11:00am A Reconfigurable Hardware Based Embedded Scheduler for Buffered Crossbar Switches Lotfi Mhamdi, Christopher Kachris and Stamatis Vassiliadis Delft University of TechnologyAn Adaptive Reed Solomon Errors-and-Erasures Decoder Lilian Atieno, Jonathan Allen, Dennis Goeckel, and Russell Tessier University of Massachusetts
A Compact FPGA Implementation of the Hash Function Whirlpool Norbert Pramstaller, Christian Rechberger, and Vincent Rijmen Graz University of Technology
12pm LunchSession 7: CAD 2 (Chair: Katherine Compton)
1:30pm Armada: Timing-Driven Pipeline-Aware Routing for FPGAs Ken Eguro and Scott Hauck University of WashingtonCombining Module Selection and Resource Sharing for Efficient FPGA Pipeline Synthesis Welson Sun, Michael J. Wirthlin, and Stephen Neuendorffer Brigham Young University
Power-Aware RAM Mapping for FPGA Embedded Memory Blocks Russell Tessier, Vaughn Betz, David Neto, and Thiagaraja Gopalsamy University of Massachusetts
2:30pm BreakSession 8: Application 3 (Chair: Jeff Arnold)
3:30pm Application-Specific Customization of Soft Processor Microarchitecture Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose University of TorontoFast and Accurate Resource Estimation of Automatically Generated Custom DFT IP Cores Peter A. Milder, Mohammad Ahmad, James C. Hoe, and Markus Pueschel Carnegie Mellon University
PS - Don't forget to register!