It's in the PCI spec. It's 2^25 clock cycles if memory serves me right.
Petter
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S
sjulhes
Hello,
We have a 2VP40 ( 15.5Mbits configuration ) to configure through a 8 bits
90ns flash by a CPLD. I try to find what time has the PCI IP to respond to PCI boot board identification process before been ignored ? This will give the time I have to configure my FPGA.
Does someone has information on this allowed time ?
Thanks.
Stéphane.
A
Austin Lesea
Petter,
I had read somewhere 80ms was all the time you had before the PCI bus was definitely allowed to ignore you (forever).
2^25 clocks is considerably longer than this. Even at 133 MHz.
Aust> "sjulhes" writes:
J
John McCaskill
For PCI 2.3, and revision 1.0a of the PCI-X spec:
100 ms from power valid to RST# high.
For PCI 2^25 clocks from RST# high to first configuration access.
For PCI-X 2^26 clocks from RST# high to first configuration access.
Regards,
John McCaskill
S
sjulhes
Thank you veru much.
Stéphane.
"John McCaskill" a écrit dans le message de news: snipped-for-privacy@f14g2000cwb.googlegroups.com...
sjulhes wrote:
For PCI 2.3, and revision 1.0a of the PCI-X spec:
100 ms from power valid to RST# high.
For PCI 2^25 clocks from RST# high to first configuration access.
For PCI-X 2^26 clocks from RST# high to first configuration access.
Regards,
John McCaskill
S
sjulhes
I just can't find it in the spec ! Can someone give me the right section ?
thanks.
Stéphane.
"John McCaskill" a écrit dans le message de news: snipped-for-privacy@f14g2000cwb.googlegroups.com...
sjulhes wrote:
For PCI 2.3, and revision 1.0a of the PCI-X spec:
100 ms from power valid to RST# high.
For PCI 2^25 clocks from RST# high to first configuration access.
For PCI-X 2^26 clocks from RST# high to first configuration access.
Regards,
John McCaskill
S
sjulhes
Ok, I found it !
But what about the PCI express ? I don't have the spec so if someone can tell me if there is the same process and what is the allowed time ?
thank you
stéphane.
"John McCaskill" a écrit dans le message de news: snipped-for-privacy@f14g2000cwb.googlegroups.com...
sjulhes wrote:
For PCI 2.3, and revision 1.0a of the PCI-X spec:
100 ms from power valid to RST# high.
For PCI 2^25 clocks from RST# high to first configuration access.
For PCI-X 2^26 clocks from RST# high to first configuration access.
Regards,
John McCaskill
K
Kolja Sulimma
sjulhes schrieb:
PCIe is hot plug capable, so it probably does not matter. Just tell the system that your device is present when you finished configuration.
Kolja Sulimma
G
Gabor
As I read the PCIe specification, it seems that the hot plug capability is optional on the system board, so this may not always work. The timing of PERST# is minimum 100ms after power stable and 100us after REFCLK stable.
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