It's in the PCI spec. It's 2^25 clock cycles if memory serves me right.
Petter
-- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
We have a 2VP40 ( 15.5Mbits configuration ) to configure through a 8 bits
90ns flash by a CPLD. I try to find what time has the PCI IP to respond to PCI boot board identification process before been ignored ? This will give the time I have to configure my FPGA.
Does someone has information on this allowed time ?
As I read the PCIe specification, it seems that the hot plug capability is optional on the system board, so this may not always work. The timing of PERST# is minimum 100ms after power stable and 100us after REFCLK stable.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.