tcam implemented in fpga

Is your cycle running at 1 MHz?

That will be a huge cam on a fpga. I quickly tried with coregen and it would take 32768 SRL16 elements. On a Virtex4 those need SLICEM elements and if I remember correctly half of the slices were M-type. So that cam would fit to a XC4VLX160. I'd guess the timing is also in the range of 25-30ns but could be much worse. The timings on the data sheets are quite optimistic usually if compared to real designs using CAMs.

I hope that the vendors would figure out better ways of using the fabric to generate CAMs (or add something to the LUTs). I woudn't mind some latency it's there also in the commercial components.

--Kim

I think two cycles are necessary! "bjzhangwn" ??????: snipped-for-privacy@g43g2000cwa.googlegroups.com...

Hi,Kim Enkovaara,You are right,The LUTs I need if the entrys is 2048 are huge,so I think if I delay the data read out(for example 4 or 5 cycles),and can the LUTs I need reduce?Thanks!And the frequency I need not too high,about 40Mhz!

The "efficient" CAM method I'm familiar with for the Xilinx silicon:

SRLs can be used as CAMs if loaded in 16 cycles to accommodate 4 bits at a time for one entry; the 4 bits of the CAM word can be 1, 0, or X giving you the Ternary CAM capability. The output from 8 of these SRLs will indicate a single 32-bit word match requiring a minimum of 16536 SRLs for the comparison itself. The 2048 "hit" signals need to be combined depending on whether you need can guarantee only one hit, need "first hit" or "longest hit" where the latter two can be ugly.

So in addition to the SRLs used for comparison, you need a mechanism that will load the SRLs in a minimum of 16 cycles per value and that will collate your 8 4-bit comparisons for each element into a single hit address.

This isn't done well with FPGAs. The alternative is to use search tables rather than rely on a TCAM which means you no longer have anything near 1 cycle performance.

Good luck in your design,

- John_H

I suppose you mean a Content Addressable Memory, normally referred to as a CAM. Search the Xilinx website. You will find, among others, XAPP201 and XAPP202, and also interfaces to external CAMs. Peter Alfke, Xilinx

"Peter Alfke" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

I guess he means Ternary CAM, and for his application its implementation in FPGA would be real huge

Antti