Field-Programmable Gate Arrays

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how to speed up the program running in ddr sdram

Hi all, At present, I am using Xilinx SPARTAN XC3S1500 FPGA with Micro MT46V16M16 to do some projects. As my programme...
3 comments posted 20yrs
posted by lnzhao
3 comments posted 20yrs posted by lnzhao

Easier initializing of blockram (spartan3)

Instead of using INIT_XX=>"...." I would like to write like "INIT(W,A)=>D" where W is the buswidth and D is the initial...
2 comments posted 20yrs
posted by mleikvol
2 comments posted 20yrs posted by mleikvol

ISE 8.1Evaluation

Does anyone know when the Evaluation version of 8.1 is going to be available to buy? TIA, Rog
5 comments posted 20yrs
posted by enquiries
5 comments posted 20yrs posted by enquiries

Downloading Nios II Eval from Altera website

Hi Sirs, For two days n a row, I've been trying to download Nios II Eval from Altera website, starting from here: https...
0 comments posted 20yrs
posted by jaac
0 comments posted 20yrs posted by jaac

Does Xilinx's step1 chips is the ES?

I am comparing 2s15 and lx25 now for a SCDMA BTS. But I heard that Xilinx's step1 chips are engineering samples and wit...
3 comments posted 20yrs
posted by mailwz
3 comments posted 20yrs posted by mailwz

spartan3 differential I/O

Hi, I have to acquire 9 couples of differential signals inside my Spartan3 fpga. How should I handle them? Should i use...
3 comments posted 20yrs
posted by marco
3 comments posted 20yrs posted by marco

Question on Alias in VHDL

I can't figure out how to use alias to create vectors of arbitary signals... What I want to do is this (Using ISE 6) si...
4 comments posted 20yrs
posted by mike
4 comments posted 20yrs posted by mike

Xilinx USB Platform Cable not working anymore

Dear, I received last week a Xilinx USB Platform Cable. Using ISE 7.1.04i and EDK 7.1.2 under Fedora core 2 with kernel...
5 comments posted 20yrs
posted by georges
5 comments posted 20yrs posted by georges

Study material for logic design

Hi All Verilog users: I am trying to find some study material to cover the basics of logic design. Actually I am prepar...
2 comments posted 20yrs
posted by salah.kazi
2 comments posted 20yrs posted by salah.kazi

Verilog to VHDL translation tool

Hi Does anyone know of a good verilog to vhdl translation tool. Thanks Sudhir
2 comments posted 20yrs
posted by Sudhir.Singh
2 comments posted 20yrs posted by Sudhir.Singh

Obsolete Xilinx Parts

If you are purchasing Xilinx parts. Check out the following website: www.mercuryintonline.com They seem to have many obs...
0 comments posted 20yrs
posted by magicsoundmm
0 comments posted 20yrs posted by magicsoundmm

"failed to create empty document"

I've been plagues lately with my machine seeming to have a limit on the number of documents or programs that can be ope...
1 comments posted 20yrs
posted by ray
1 comments posted 20yrs posted by ray

concurrent auto precharge - memory controller

Hi all, I am designing a memory controller and I want to use concurrent auto precharge. I am using a micron SDR-SDRAM (...
4 comments posted 20yrs
posted by subhasri.krishnan
4 comments posted 20yrs posted by subhasri.krishnan

Synthesis and EDIF gurus.....

I have an EDK project with a bunch of Xilinx cores and a bunch of custom cores. All the custom cores are attached to th...
1 comments posted 20yrs
posted by mottoblatto
1 comments posted 20yrs posted by mottoblatto

newbie question about Xillinx JTAG cable

Hello guys, I have a JTAG cable with 1 line female output, but my board has only 2 lines- pins connector for JTAG. So,...
1 comments posted 20yrs
posted by frankschr
1 comments posted 20yrs posted by frankschr