Xilinx Routing & Clock/Data Skew

I am working on a timing simulation of an array of source synchronous flip-flops with all D inputs connected to the same net. The design requires a small (~10ps) skew between the arrival of the clock to each F/F. In regards to this topology I have several questions:

2) In operation, what degree of changes in skew can be expected? (The simulator specifies skews of 5ps to 100ps between succssive F/F's what range of values can be expected in operation?).

Thanks, Brendan