Field-Programmable Gate Arrays

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About Altera FPGA Board

There are three sets of holes for accessing signal I/O pins on the altera fpga board ...they are flex_expan_A,B and C o...
10 comments posted 20yrs
posted by laura_pretty05
10 comments posted 20yrs posted by laura_pretty05

How do I handle this memory related issue?

I received a design from a vendor, which is designed for Virtex 2 FPGA. In the design there are four instances of RAMs,...
4 comments posted 20yrs
posted by novice
4 comments posted 20yrs posted by novice

debuging power_pc + microblaze

Hi all, Can I create an EDK based system containing both a PPC and MB while connecting debug peripheral to both of them...
0 comments posted 20yrs
posted by me_2003
0 comments posted 20yrs posted by me_2003

PROBLEMS WITH COOLRUNNER XPLA3

hi im using digilab XCR development board which has Xilinx XCR3064 CPLD. I/O pins in this CPLD are said to be tristate....
5 comments posted 20yrs
posted by sachink321
5 comments posted 20yrs posted by sachink321

Soldering SMT/BGA

Hi, I'm very new to fpga, just came interrested in these things. The only problem I think I will have is the soldering....
23 comments posted 20yrs
posted by msn
23 comments posted 20yrs posted by msn

Why does Xilinx hate version control?

Is there some internal Xilinx conspiracy against source code management like SVN (subversion) and CVS? Or is it that th...
38 comments posted 20yrs
posted by jakeREMOVEjanovetz
38 comments posted 20yrs posted by jakeREMOVEjanovetz

Doubt on the xilinx Viretex E user guide

In the 9th page of VirtexE user guide ds022.pdf it is said that the VirtexE LUTs can be used as 16x1 RAM. How can an LU...
3 comments posted 20yrs
posted by vssumesh_asic
3 comments posted 20yrs posted by vssumesh_asic

FPGA Design Implementation

hi folks, can you recommend a book on FPGA design implementation, that touches the following issues: -floorplanning (me...
1 comments posted 20yrs
posted by dfroehli
1 comments posted 20yrs posted by dfroehli

Xilinx DDR SDRAM Controller

I am having a difficulty grasping project structure, generated by Xilinx MIG007 software. I?ve generated 16-bit data DD...
1 comments posted 20yrs
posted by norvilis
1 comments posted 20yrs posted by norvilis

How to specify a package in Xilinx 8.1i

Hi, I need your help. I have 4 vhdl source files: A-Package.vhd; A1.vhd; A2.vhd; A3.vhd; A-Package.vhd is a package def...
1 comments posted 20yrs
posted by wtxwtx
1 comments posted 20yrs posted by wtxwtx

using EDK with the gcc -g option...

Hi all, I have a little question regarding gcc, does the -g option for the mb-gcc/powerpc-gcc compiler makes the execut...
10 comments posted 20yrs
posted by me_2003
10 comments posted 20yrs posted by me_2003

Question about multi write ports RAM in FPGA?

Hello, Is that possible to make a multi write ports RAM in FPGA by using distributed RAM or block RAM? It seems impossi...
24 comments posted 20yrs
posted by hy34
24 comments posted 20yrs posted by hy34