hi im using digilab XCR development board which has Xilinx XCR3064 CPLD. I/O pins in this CPLD are said to be tristate. but when im trying to use them as tristate its not working as one? i mean i want one of the I/O pin to go high impedance but its not? can any one tell me how can i make I/O pin in CPLD high impedance?
Post the code that drives the outputs... And what does the synthesiser say? B
Using VHDL:
io_pin
thers no problem with synthesizer nor simulation results infact simulation results show the output in high impedance but when i check(using logic probe) that on hardware its not in high impedance
code is simple
2 inputs ( switches) 1 output (I/O pin)dout Post the code that drives the outputs...
Ummmm, how is the logic probe supposed to know that the pin is tristated?
-a
schrieb im Newsbeitrag news: snipped-for-privacy@z34g2000cwc.googlegroups.com...
Fitter standard I/O termination is bus keeper. You can select pullup or float.
If you float the pins (in the implementaion-fitter properties), you must insure, that no input pin is unconnected and floating.
MIKE
-- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho !
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