Coregen in ISE 8.1i webpack not working quite right

Hello everyone, I managed to snag one of the freebie Xilinx Spartan 3e sample pack boards, and while the board came with ISE 7.1, I discovered the ISE 8.1 Webpack came with a lot of nice extras, like coregen.

The problem is that a lot of the IP's in the coregen don't work. I checked the app note about paths with spaces in them, and reinstalled to a folder that didn't have any. (I installed ISE to C:\projects\xilinx). The project I'm working on is in C:\projects\cores. Based on that, it appears the note is no longer applicable.

Except that I still see an error message when I try to create certain cores: "ERROR:coreutil:4 - Couldn't open "C:\Projects\FPGA Stuff\Playground\Cores\tmp\_cg\" for writing."

I also checked the Java memory allocation, and set it to 512Mb, although it doesn't seem to matter. (I saw an app note about memory allocation on NT based systems - and I'm using Windows XP)

The weird part is that some things work fine, and others don't. For example, I can create a FIFO, but not a block memory. I can build a floating point unit, but not a MAC.

Has anyone else seen this?



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If there is a space between "Projects\FPGA" and "Stuff\...", then some of the tools will break.

No spaces, it should work.

-- Phil Hays

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Phil Hays


I moved the coregen project file to C:\Projects\Cores to avoid the spaces, but I didn't realize it stored the path in the project file. I edited the path in the .cgp, and everything is working.

The error should have been a hint...

Oh well, I'm still learning ISE. I've used Altera MaxPlusII or Quartus my entire career - this is my first Xilinx based design.


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