In the 9th page of VirtexE user guide ds022.pdf it is said that the VirtexE LUTs can be used as 16x1 RAM. How can an LUT be used as RAM. I think the content of the LUT is written at the time of burning the FPGA. Is this an error or is there any way we can change the configuration of the LUT dynamically. regards Sumesh V S
This is not an error. The four input LUT consists of 16 memory locations, the value of which is loaded from the configuration bitstream. It can be configured in a number of modes:
- LUT. This is like a 16 entry ROM.
- RAM. Like the LUT, but with the ability to write a bit to a location.
- SRL. This turns the 16 memory locations into a 16 bit shift register.
The mode of the LUT can't change without reconfiguring the FPGA. The contents of the LUT can be changed any time if in RAM or SRL modes.
Regards, Allan
Thanks Allan, found an entry the verilog template provided with Xilinx ISE. But in that is instantiated as a primitive module. Is there any way we can instantiate it indirectly using verilog code.
Various RAMs can be instantiated or inferred from your source code. You should read the XST manual - it will show you how.
Regards, Allan
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.