Doubt on the xilinx Viretex E user guide

This is not an error. The four input LUT consists of 16 memory locations, the value of which is loaded from the configuration bitstream. It can be configured in a number of modes:

- LUT. This is like a 16 entry ROM.

- RAM. Like the LUT, but with the ability to write a bit to a location.

- SRL. This turns the 16 memory locations into a 16 bit shift register.

The mode of the LUT can't change without reconfiguring the FPGA. The contents of the LUT can be changed any time if in RAM or SRL modes.

Regards, Allan

Thanks Allan, found an entry the verilog template provided with Xilinx ISE. But in that is instantiated as a primitive module. Is there any way we can instantiate it indirectly using verilog code.

Various RAMs can be instantiated or inferred from your source code. You should read the XST manual - it will show you how.

Regards, Allan