Latest threads in Field-Programmable Gate Arrays

Question about multi write ports RAM in FPGA?

Hello, Is that possible to make a multi write ports RAM in FPGA by using distributed RAM or block RAM? It seems impossi...

24 20yrs

hy34

24 20yrs hy34

LEON processor core

I'm wondering why there are so few messages about LEON [1] in this group. LEON looks like a very solid design (used by...

10 20yrs

mschoebe

10 20yrs mschoebe

Have webpack-81i running on grml Linux, rewrote ppcableIII jtag driver for Digilent to use direct io.

I got a Linux distro from www.grml.org, and have the 8.1 webpack working on it. This is a small distro, and I think it...

1 20yrs

pNaonStpealmtje

1 20yrs pNaonStpealmtje

Plateform FLASH PROM configuration using a Microblaze.

Hello all, In a project, I use a Spartan-3 XC3S400 FPGA from Xilinx. The design use a Microblaze CPU instantiated in th...

13 20yrs

claudesylvain

13 20yrs claudesylvain

ModelSim 6.0 v 5.7 Can't read file

When I upgrade(?) to ISE 7.1.4 and ModelSim 6.0 I find my testbenches can not read binary files. Is this a technical pr...

3 20yrs

bradsmallridge

3 20yrs bradsmallridge

synthesis time with XST

Hello, I'm using ISE 8.1 and I'm facing problems to synthesize my VHDL project. This project was simulated in modsim wi...

6 20yrs

fabio.rocha

6 20yrs fabio.rocha

AC97 Codec

Hi, I plan to do a project using the AC97 codec on a Virtex-II Pro board. I'm thinking to read inputs from MIC, do some...

0 20yrs

dasani8888

0 20yrs dasani8888

Z80 Support Cores

Was just wondering if there were any cores out there ( not for a commercial product, just hobby experimentation here )...

0 20yrs

ziggy

0 20yrs ziggy

EDK8.1: Is adding IP core parameters stiil possible?

In EDK7.1 I could easily add any parameters to any of the IP cores. I can't find how this is done in 8.1... Is it still...

5 20yrs

mbmsv

5 20yrs mbmsv

Someone need to port LwIP to ll_temac core/wrapper?

Hallo, I have contacted GRSD team, the Xilinx developers of ll_temac, ll_gemac and multiport memory controller about po...

7 20yrs

marc

7 20yrs marc

Learning new stuff about FPGA

Hi everybody, I am beginner in FPGA design ( about 1 year of experience in VHDL design), I enjoy my job but (there is a...

3 20yrs

KCLO4[no_spam]

3 20yrs KCLO4[no_spam]

Call for Papers with extended deadline: IMECS 2006 (the multiconference of 14 engineering & computer science conferences)

Extended CFP From: International Association of Engineers (http://www.iaeng.org) Engineering Letters (http://www.engine...

0 20yrs

imecs_2006

0 20yrs imecs_2006

EDK: DCR bus doesn't work

Dear EDK experts, Here I am again with an EDK problem... I have a top level ISE design and an EDK submodule (PPC). I am...

1 20yrs

mbmsv

1 20yrs mbmsv

Problems with Output pins on XUP board

Hey, I'm trying to connect my VHDL core of a PLB bus master to two LEDs to aid me in debugging the hardware as I'm usin...

1 20yrs

jda59

1 20yrs jda59

a problem with coolrunner CPLD (XC2C256) GCK0 pin

Hello Dear friends The board we have designed uses of XC2C256 in its center which distributes and switches between diff...

12 20yrs

arash_majd

12 20yrs arash_majd

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