Field-Programmable Gate Arrays

LEON processor core

I'm wondering why there are so few messages about LEON [1] in this group. LEON looks like a very solid design (used by...

10 comments posted 20yrs

posted by mschoebe

10 comments posted 20yrs posted by mschoebe

Have webpack-81i running on grml Linux, rewrote ppcableIII jtag driver for Digilent to use direct io.

I got a Linux distro from www.grml.org, and have the 8.1 webpack working on it. This is a small distro, and I think it...

1 comments posted 20yrs

posted by pNaonStpealmtje

1 comments posted 20yrs posted by pNaonStpealmtje

Plateform FLASH PROM configuration using a Microblaze.

Hello all, In a project, I use a Spartan-3 XC3S400 FPGA from Xilinx. The design use a Microblaze CPU instantiated in th...

13 comments posted 20yrs

posted by claudesylvain

13 comments posted 20yrs posted by claudesylvain

ModelSim 6.0 v 5.7 Can't read file

When I upgrade(?) to ISE 7.1.4 and ModelSim 6.0 I find my testbenches can not read binary files. Is this a technical pr...

3 comments posted 20yrs

posted by bradsmallridge

3 comments posted 20yrs posted by bradsmallridge

synthesis time with XST

Hello, I'm using ISE 8.1 and I'm facing problems to synthesize my VHDL project. This project was simulated in modsim wi...

6 comments posted 20yrs

posted by fabio.rocha

6 comments posted 20yrs posted by fabio.rocha

AC97 Codec

Hi, I plan to do a project using the AC97 codec on a Virtex-II Pro board. I'm thinking to read inputs from MIC, do some...

0 comments posted 20yrs

posted by dasani8888

0 comments posted 20yrs posted by dasani8888

Z80 Support Cores

Was just wondering if there were any cores out there ( not for a commercial product, just hobby experimentation here )...

0 comments posted 20yrs

posted by ziggy

0 comments posted 20yrs posted by ziggy

EDK8.1: Is adding IP core parameters stiil possible?

In EDK7.1 I could easily add any parameters to any of the IP cores. I can't find how this is done in 8.1... Is it still...

5 comments posted 20yrs

posted by mbmsv

5 comments posted 20yrs posted by mbmsv

Someone need to port LwIP to ll_temac core/wrapper?

Hallo, I have contacted GRSD team, the Xilinx developers of ll_temac, ll_gemac and multiport memory controller about po...

7 comments posted 20yrs

posted by marc

7 comments posted 20yrs posted by marc

Learning new stuff about FPGA

Hi everybody, I am beginner in FPGA design ( about 1 year of experience in VHDL design), I enjoy my job but (there is a...

3 comments posted 20yrs

posted by KCLO4[no_spam]

3 comments posted 20yrs posted by KCLO4[no_spam]

Call for Papers with extended deadline: IMECS 2006 (the multiconference of 14 engineering & computer science conferences)

Extended CFP From: International Association of Engineers (http://www.iaeng.org) Engineering Letters (http://www.engine...

0 comments posted 20yrs

posted by imecs_2006

0 comments posted 20yrs posted by imecs_2006

EDK: DCR bus doesn't work

Dear EDK experts, Here I am again with an EDK problem... I have a top level ISE design and an EDK submodule (PPC). I am...

1 comments posted 20yrs

posted by mbmsv

1 comments posted 20yrs posted by mbmsv

Problems with Output pins on XUP board

Hey, I'm trying to connect my VHDL core of a PLB bus master to two LEDs to aid me in debugging the hardware as I'm usin...

1 comments posted 20yrs

posted by jda59

1 comments posted 20yrs posted by jda59

a problem with coolrunner CPLD (XC2C256) GCK0 pin

Hello Dear friends The board we have designed uses of XC2C256 in its center which distributes and switches between diff...

12 comments posted 20yrs

posted by arash_majd

12 comments posted 20yrs posted by arash_majd

Nios2 and Shared Bus Resources

On a project I am working on, I recently had the requirement of embedding an ethernet controller into the system. Since...

0 comments posted 20yrs

posted by no_spam_me2

0 comments posted 20yrs posted by no_spam_me2