I received a design from a vendor, which is designed for Virtex 2 FPGA. In the design there are four instances of RAMs, which are of DPRAMs of
16bX4096w each. (In fact, there are no WRITE events to these RAMs throughout simulations.)In the test bench, a FOR loop reads in some ASCII files and pumps into RAMs at beginning of each simulation.
Now when I convert this portion into ASIC using library RAMs, how should I take care of this?
Thank you for your comments.
If it is never written it is rom not ram ....
-Lasse
Agree with that, but in the simulations I studied so far, there are R/W data/address and enable connections in the RTL code, and instantiated a coregen DPRAM.
Did fair large numbers of coregen RAMs in FPGA before, but now when it comes to ASIC, I am a bit blur. AFAIK, there is no ROM cells in my ASIC library.
Depends on the library. Usually ASIC memory models have features to read data in as file images (to speed up the simulations). Or use the same method as in the FPGA. You just have little different memory model to represent the memory. But still at the bottom you have some memory array where the data is stored. In some asic libraries bisr etc. makes the models quite complex but...
If that data is static (no writes to the memory) then you have a rom. Pick a rom model from the asic memory generator. If that is not supported directly in the generator, you have to ask from the vendor how they want roms implemented.
This all should be covered in the vendor documentation, if you just read it :)
--Kim
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