Xilinx DDR SDRAM Controller

I am having a difficulty grasping project structure, generated by Xilinx MIG007 software. I?ve generated 16-bit data DDR1 SDRAM interface to Spartan3 xc3s500-4-efg208 device. MIG user manual describes user signal interface and timing for ddr1_top which is the main DDR SDRAM controller. But it?s hierarchically below ddr1_test and mem_interface_top modules. These probably enhance user interface or could be used for controller testing, I just can?t find any documentation regarding their use. MIG007 also generated startup_spartan3 module, but here again no information on how to use it. I?d like to have a simple SRAM like user interface. If someone?s done this, I would appreciate some pointers.

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Remis Norvilis
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I am too trying to get a DDR controller up and running on a Spartan 3 and have found MIG to be very frustrating. At the moment I am looking at the DDR controller on opencores and have got it simulating under modelsim. Not sure how easy it will be to get going on real hardware though. I have posted a few messages on here regarding DDR and havent really got any replies so either people are having trouble getting it working or are keeping quiet


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