Field-Programmable Gate Arrays

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Storing variables into data ocm memory

Hallo, I' developing a microcontroller based on powerpc. the only way I know to store some variables into a specific re...
2 comments posted 20yrs
posted by marc
2 comments posted 20yrs posted by marc

Cyclone II EP2C70 dev kits, where are they?

Having just realized that ISE WebPack support ends at an XC3S1500 I set out to locate a Cyclone II EP2C70 based dev kit...
9 comments posted 20yrs
posted by foobar
9 comments posted 20yrs posted by foobar

how to immitate clock behavior----Please guide

Please help! The code for Viterbi decoder that i have written, is not giving ERRORS during synthesis but is having like...
2 comments posted 20yrs
posted by preet723
2 comments posted 20yrs posted by preet723

Keystroke saving w/ IEEE.Numeric_Std

When you want a one of eight decoder, are you tired of typing in: with Phase_Ctr select Phase
4 comments posted 20yrs
posted by john.l.smith
4 comments posted 20yrs posted by john.l.smith

xst and fpga express

Hi all, i am working in a network security company..i got a question.. am using a very big design targeted for xilinx v...
0 comments posted 20yrs
posted by uckingcu
0 comments posted 20yrs posted by uckingcu

basic doubts about chipscope pro

Hi all, The design that I am working on is becoming increasingly difficult to debug and so I am trying to use chipscope...
4 comments posted 20yrs
posted by subhasri.krishnan
4 comments posted 20yrs posted by subhasri.krishnan

combinatorial always blocks + for-loops in XST

All- I'm using Spartan 3 + XST 7.1sp4. In the code below, is there a way to use a combinatorial always block and a for-...
10 comments posted 20yrs
posted by jbrower
10 comments posted 20yrs posted by jbrower

Specifying top level generics with XST 7.1

Hello, We have a parameterizable (via top level generics) VHDL design that we are trying to put into an FPGA using the...
2 comments posted 20yrs
posted by moogyd
2 comments posted 20yrs posted by moogyd

actmap looks like not responding

im a final year student, and im trying to synthesis my floating point adder. This has so many small modules, everything...
1 comments posted 20yrs
posted by praviendre
1 comments posted 20yrs posted by praviendre

Bidirectional signals with Altera Signaltap

Dear all, I am trying to using SignalTap to debug a design in which I have some bidirectional ports. Using both Pre-syn...
2 comments posted 20yrs
posted by gvaglia
2 comments posted 20yrs posted by gvaglia

OPB monitor error

Hi all, I'm currently verifying an OPB master i/f using IBM's OPB monitor. I'm currently getting an error 1.11.3, which...
7 comments posted 20yrs
posted by dumak23
7 comments posted 20yrs posted by dumak23

Please recomend textbook with AES encryption.

Hi, there: I am looking for textbook with detailed information on AES encryption and decryption. I have Bernard Sklar's...
3 comments posted 20yrs
posted by frank
3 comments posted 20yrs posted by frank