EDK/Xilinx : Insertion of ECC capability into BRAM controller

Greetings.

I am looking to figure out a way to modify an existing BRAM controller (connected to either OPB or PLB) to add ECC capabilities. I am using EDK 7.1i, and it appears that controllers instantiated there cannot be modified. I have looked at Xilinx XAPP645 and understand how it works, but can't find a way to insert the VHDL into an existing controller.

Basically, I'm trying to break the connection at PORTA such that the data will run through the ECC encoder to the BRAM, but the address and control lines are still intact (and connected to to the BRAM blocks). It seems like it should be a fairly straightforward exercise, but I have had zero success.

The other part of the issue is that BRAM itself appears to be instantiated as part of the controller, so I also need to have a way to support the extra data as well. I appear to be getting BRAMs with the additional bit for parity data, but have no good way to access it.

This is being done on a Virtex-II Pro, and I'm connecting to the PPC core. However, I don't think this is application-specific, since I should be able to do the same thing with a Microblaze, for example.

Thanks!

Hi Jon,

The VHDL for the Xilinx BRAM controller is provided with the EDK. Look in C:\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b (or wherever you installed the EDK on your machine). There's a similar core for the OPB, and a base library in bram_if_cntlr_v1_00_b

You should be able to copy and merge the appropriate folders and use it as a custom core in your own EDK project. You'll probably want to pick a new core name instead of plb_bram_if_cntlr to avoid confusion. Be sure to rename all of the appropriate files. (I found this to be a big pain to get right if you've never made a custom core before. You could use the Xilinx wizard to create an empty PLB or OPB core and use it as an example of their naming and version number conventions.)

The BRAM is not instantiated as part of the controller. You use the separate bram_block core in the EDK for it. You should be able to copy that core as well and modify it if needed. Also, you should be able to find examples of how the controller and BRAM core are connected. There are plenty of basic examples of a PowerPC, PLB bus, controller, and BRAM memory available online.

Hope this helps,

Jeff