im a final year student, and im trying to synthesis my floating point adder. This has so many small modules, everything was synthesised and they are ok.
My problem is the when im trying to synthesis the top design which combines all the small modules it looks like the actmap programme is not responding.
It goes fine until the
Logic Optimization and Mapping for (fpAdderSub)
BDD based synthesis BDD synthesis skipped
Library based synthesis
i think it looks like it has stuck after the Library based synthesis. Because it doesn't performs any further action. i have waited like 60 minutes.
any ideas??? pls reply !!! Thanks a lot.