Latest threads in Field-Programmable Gate Arrays

Hand-drawn schematic symbols of ISE coregen cores revert to rectangles when underlying core parameters are changed!

Hi All, My design flow includes a top-level schematic into which I place symbols which represent lower-level modules, i...

2 20yrs

peter

2 20yrs peter

WARNING:Xst:1778 - Inout <AddrBus>

Hi, I am getting the following warning: WARNING:Xst:1778 - Inout is assigned but never used. My AddrBus is bi-direction...

5 20yrs

bobrics

5 20yrs bobrics

ERROR:Xst:827 - bad synchronous description

Hi, I have a problem synthesizing a VHDL code. The error is the following: ERROR:Xst:827 - "C:/Xilinx/work/MYPROJECT/pr...

2 20yrs

bobrics

2 20yrs bobrics

deglitching a clock

We have a perfect-storm clock problem. A stock 16 MHz crystal oscillator drives a CPU and two Spartan3 FPGAs. The chips...

85 20yrs

jjlarkin

85 20yrs jjlarkin

OPB IPIF Master Support

Hi everyone, I am building a OPB peripheral. I used Create - Import Peripheral wizard from EDK 7.1 (using opb_ipif_v2_0...

0 20yrs

ales.gorkic

0 20yrs ales.gorkic

Opb Spi Controller Trouble

Hallo, I have added opb_spi 1.00.d to my design. It is a microcontroller based on powerpc. I have connected the ports:...

0 20yrs

marc

0 20yrs marc

Variable Bus Input/Output Fifo

Has anyone ever written a variable width fifo? I would like to have a fifo that accepts a 32-bit input and reads out a 1...

2 20yrs

dominicwalkes

2 20yrs dominicwalkes

spartan FPGA with PLCC package

Hi, is any spartan FPGA is in PLCC package?also its availabilty ? I want to use spartan series FPGA & not the any other...

9 20yrs

kulkarku

9 20yrs kulkarku

Linux on ml403

Hi, I have been trying to port Linux on the ML403 board using the 2.4 devel tree downloaded from montavista site using...

6 20yrs

jean-francois.hasson

6 20yrs jean-francois.hasson

Spartan 3e Starter Kit finally available? No, not really.

For the past week or so the Xilinx online store says that target availability (from the store) is April, but that it is...

4 20yrs

eric

4 20yrs eric

Clock multiplication without using the Xilinx DCM's

Hi, We are developing a product that passes data between an xDSL interface and a proprietory optical interface. We are...

14 20yrs

andrew.newsgroup

14 20yrs andrew.newsgroup

Altera web site inaccessible

The Altera web site has been inaccessible now for over 48 hours. Further investigation this evening shows that only cer...

26 20yrs

MikeShepherd564

26 20yrs MikeShepherd564

need help,test on Spartan3 starter kit

Hi, Please someone help me. As a school project i am designing a Viterbi Decoder, now i have to test it on FPGA. Please...

4 20yrs

preet723

4 20yrs preet723

EDK 8.1 Problem: Adding .h or .c files ?

Hello everybody, Starting with the Xilinx Microblaze Examples, I'd like to add my own .h and .c files with function dec...

0 20yrs

Ben.Marpe

0 20yrs Ben.Marpe

ERROR:NgdBuild:604

Hi I have made a new IP using the create or import peripheral wizard. When I add my own logic to this IP I get this err...

4 20yrs

michiel.vanderlinden

4 20yrs michiel.vanderlinden

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