Field-Programmable Gate Arrays

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WARNING:Xst:1778 - Inout <AddrBus>

Hi, I am getting the following warning: WARNING:Xst:1778 - Inout is assigned but never used. My AddrBus is bi-direction...
5 comments posted 20yrs
posted by bobrics
5 comments posted 20yrs posted by bobrics

ERROR:Xst:827 - bad synchronous description

Hi, I have a problem synthesizing a VHDL code. The error is the following: ERROR:Xst:827 - "C:/Xilinx/work/MYPROJECT/pr...
2 comments posted 20yrs
posted by bobrics
2 comments posted 20yrs posted by bobrics

deglitching a clock

We have a perfect-storm clock problem. A stock 16 MHz crystal oscillator drives a CPU and two Spartan3 FPGAs. The chips...
85 comments posted 20yrs
posted by jjlarkin
85 comments posted 20yrs posted by jjlarkin

OPB IPIF Master Support

Hi everyone, I am building a OPB peripheral. I used Create - Import Peripheral wizard from EDK 7.1 (using opb_ipif_v2_0...
0 comments posted 20yrs
posted by ales.gorkic
0 comments posted 20yrs posted by ales.gorkic

Opb Spi Controller Trouble

Hallo, I have added opb_spi 1.00.d to my design. It is a microcontroller based on powerpc. I have connected the ports:...
0 comments posted 20yrs
posted by marc
0 comments posted 20yrs posted by marc

Variable Bus Input/Output Fifo

Has anyone ever written a variable width fifo? I would like to have a fifo that accepts a 32-bit input and reads out a 1...
2 comments posted 20yrs
posted by dominicwalkes
2 comments posted 20yrs posted by dominicwalkes

spartan FPGA with PLCC package

Hi, is any spartan FPGA is in PLCC package?also its availabilty ? I want to use spartan series FPGA & not the any other...
9 comments posted 20yrs
posted by kulkarku
9 comments posted 20yrs posted by kulkarku

Linux on ml403

Hi, I have been trying to port Linux on the ML403 board using the 2.4 devel tree downloaded from montavista site using...
6 comments posted 20yrs
posted by jean-francois.hasson
6 comments posted 20yrs posted by jean-francois.hasson

Clock multiplication without using the Xilinx DCM's

Hi, We are developing a product that passes data between an xDSL interface and a proprietory optical interface. We are...
14 comments posted 20yrs
posted by andrew.newsgroup
14 comments posted 20yrs posted by andrew.newsgroup

Altera web site inaccessible

The Altera web site has been inaccessible now for over 48 hours. Further investigation this evening shows that only cer...
26 comments posted 20yrs
posted by MikeShepherd564
26 comments posted 20yrs posted by MikeShepherd564

need help,test on Spartan3 starter kit

Hi, Please someone help me. As a school project i am designing a Viterbi Decoder, now i have to test it on FPGA. Please...
4 comments posted 20yrs
posted by preet723
4 comments posted 20yrs posted by preet723

EDK 8.1 Problem: Adding *.h or *.c files ?

Hello everybody, Starting with the Xilinx Microblaze Examples, I'd like to add my own .h and .c files with function dec...
0 comments posted 20yrs
posted by Ben.Marpe
0 comments posted 20yrs posted by Ben.Marpe

ERROR:NgdBuild:604

Hi I have made a new IP using the create or import peripheral wizard. When I add my own logic to this IP I get this err...
4 comments posted 20yrs
posted by michiel.vanderlinden
4 comments posted 20yrs posted by michiel.vanderlinden

chip reverse engineering

regards is it possible from the driver of a chip and pin assignment of a chip to reverse a chip,and to produce the same...
9 comments posted 20yrs
posted by mikeotp
9 comments posted 20yrs posted by mikeotp