Question about: Logic Levels in Critical Path

Hello here, I have a 64bits adder (ALU) like this c

Reply to
hongyan
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Hi, If this is a Xilinx design, try looking at the design in the timing analyser tool. It will show the logic levels, and you should be able to work out what's going on. HTH, and good luck, Syms.

Reply to
Symon

Symon schrieb:

Hi Symon two more tips:

1) How about the wire delays at the inputs? Are they reduced when you use registers?

2) Is your tool performing some sort of register balancing for timing improvement? This may cause portions of the adder to be placed before the registers thus reducing the logic levels of the adder itself.

have a nice synthesis Eilert

Reply to
backhus
1) No, they didn't. Because I did all the synthesis without I/O package. So for the adder itself, there is no time delay for the input signals. And If I add register before that, there will be some Dff gate delay and wiring delay.

2) In XST, I didn't use register balancing but I still got less logic levels. In synplifypro, its seems there is no such option. And I don't know if the register balancing is a default operation or not.

Thank you for your reply.

Reply to
hongyan

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